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337 lines
9.0 KiB
337 lines
9.0 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* AppliedMicro X-Gene SoC GPIO-Standby Driver |
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* |
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* Copyright (c) 2014, Applied Micro Circuits Corporation |
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* Author: Tin Huynh <[email protected]>. |
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* Y Vo <[email protected]>. |
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* Quan Nguyen <[email protected]>. |
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*/ |
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#include <linux/module.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/acpi.h> |
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#include "gpiolib.h" |
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#include "gpiolib-acpi.h" |
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/* Common property names */ |
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#define XGENE_NIRQ_PROPERTY "apm,nr-irqs" |
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#define XGENE_NGPIO_PROPERTY "apm,nr-gpios" |
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#define XGENE_IRQ_START_PROPERTY "apm,irq-start" |
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#define XGENE_DFLT_MAX_NGPIO 22 |
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#define XGENE_DFLT_MAX_NIRQ 6 |
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#define XGENE_DFLT_IRQ_START_PIN 8 |
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#define GPIO_MASK(x) (1U << ((x) % 32)) |
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#define MPA_GPIO_INT_LVL 0x0290 |
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#define MPA_GPIO_OE_ADDR 0x029c |
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#define MPA_GPIO_OUT_ADDR 0x02a0 |
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#define MPA_GPIO_IN_ADDR 0x02a4 |
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#define MPA_GPIO_SEL_LO 0x0294 |
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#define GPIO_INT_LEVEL_H 0x000001 |
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#define GPIO_INT_LEVEL_L 0x000000 |
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/** |
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* struct xgene_gpio_sb - GPIO-Standby private data structure. |
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* @gc: memory-mapped GPIO controllers. |
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* @regs: GPIO register base offset |
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* @irq_domain: GPIO interrupt domain |
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* @irq_start: GPIO pin that start support interrupt |
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* @nirq: Number of GPIO pins that supports interrupt |
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* @parent_irq_base: Start parent HWIRQ |
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*/ |
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struct xgene_gpio_sb { |
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struct gpio_chip gc; |
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void __iomem *regs; |
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struct irq_domain *irq_domain; |
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u16 irq_start; |
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u16 nirq; |
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u16 parent_irq_base; |
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}; |
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#define HWIRQ_TO_GPIO(priv, hwirq) ((hwirq) + (priv)->irq_start) |
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#define GPIO_TO_HWIRQ(priv, gpio) ((gpio) - (priv)->irq_start) |
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static void xgene_gpio_set_bit(struct gpio_chip *gc, |
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void __iomem *reg, u32 gpio, int val) |
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{ |
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u32 data; |
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data = gc->read_reg(reg); |
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if (val) |
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data |= GPIO_MASK(gpio); |
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else |
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data &= ~GPIO_MASK(gpio); |
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gc->write_reg(reg, data); |
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} |
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static int xgene_gpio_sb_irq_set_type(struct irq_data *d, unsigned int type) |
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{ |
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struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d); |
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int gpio = HWIRQ_TO_GPIO(priv, d->hwirq); |
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int lvl_type = GPIO_INT_LEVEL_H; |
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switch (type & IRQ_TYPE_SENSE_MASK) { |
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case IRQ_TYPE_EDGE_RISING: |
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case IRQ_TYPE_LEVEL_HIGH: |
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lvl_type = GPIO_INT_LEVEL_H; |
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break; |
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case IRQ_TYPE_EDGE_FALLING: |
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case IRQ_TYPE_LEVEL_LOW: |
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lvl_type = GPIO_INT_LEVEL_L; |
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break; |
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default: |
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break; |
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} |
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xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO, |
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gpio * 2, 1); |
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xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_INT_LVL, |
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d->hwirq, lvl_type); |
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/* Propagate IRQ type setting to parent */ |
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if (type & IRQ_TYPE_EDGE_BOTH) |
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return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING); |
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else |
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return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); |
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} |
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static struct irq_chip xgene_gpio_sb_irq_chip = { |
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.name = "sbgpio", |
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.irq_eoi = irq_chip_eoi_parent, |
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.irq_mask = irq_chip_mask_parent, |
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.irq_unmask = irq_chip_unmask_parent, |
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.irq_set_type = xgene_gpio_sb_irq_set_type, |
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}; |
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static int xgene_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio) |
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{ |
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struct xgene_gpio_sb *priv = gpiochip_get_data(gc); |
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struct irq_fwspec fwspec; |
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if ((gpio < priv->irq_start) || |
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(gpio > HWIRQ_TO_GPIO(priv, priv->nirq))) |
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return -ENXIO; |
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fwspec.fwnode = gc->parent->fwnode; |
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fwspec.param_count = 2; |
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fwspec.param[0] = GPIO_TO_HWIRQ(priv, gpio); |
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fwspec.param[1] = IRQ_TYPE_EDGE_RISING; |
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return irq_create_fwspec_mapping(&fwspec); |
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} |
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static int xgene_gpio_sb_domain_activate(struct irq_domain *d, |
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struct irq_data *irq_data, |
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bool reserve) |
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{ |
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struct xgene_gpio_sb *priv = d->host_data; |
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u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq); |
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int ret; |
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ret = gpiochip_lock_as_irq(&priv->gc, gpio); |
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if (ret) { |
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dev_err(priv->gc.parent, |
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"Unable to configure XGene GPIO standby pin %d as IRQ\n", |
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gpio); |
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return ret; |
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} |
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xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO, |
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gpio * 2, 1); |
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return 0; |
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} |
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static void xgene_gpio_sb_domain_deactivate(struct irq_domain *d, |
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struct irq_data *irq_data) |
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{ |
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struct xgene_gpio_sb *priv = d->host_data; |
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u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq); |
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gpiochip_unlock_as_irq(&priv->gc, gpio); |
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xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO, |
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gpio * 2, 0); |
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} |
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static int xgene_gpio_sb_domain_translate(struct irq_domain *d, |
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struct irq_fwspec *fwspec, |
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unsigned long *hwirq, |
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unsigned int *type) |
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{ |
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struct xgene_gpio_sb *priv = d->host_data; |
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if ((fwspec->param_count != 2) || |
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(fwspec->param[0] >= priv->nirq)) |
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return -EINVAL; |
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*hwirq = fwspec->param[0]; |
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*type = fwspec->param[1]; |
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return 0; |
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} |
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static int xgene_gpio_sb_domain_alloc(struct irq_domain *domain, |
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unsigned int virq, |
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unsigned int nr_irqs, void *data) |
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{ |
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struct irq_fwspec *fwspec = data; |
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struct irq_fwspec parent_fwspec; |
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struct xgene_gpio_sb *priv = domain->host_data; |
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irq_hw_number_t hwirq; |
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unsigned int i; |
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hwirq = fwspec->param[0]; |
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for (i = 0; i < nr_irqs; i++) |
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irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, |
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&xgene_gpio_sb_irq_chip, priv); |
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parent_fwspec.fwnode = domain->parent->fwnode; |
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if (is_of_node(parent_fwspec.fwnode)) { |
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parent_fwspec.param_count = 3; |
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parent_fwspec.param[0] = 0;/* SPI */ |
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/* Skip SGIs and PPIs*/ |
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parent_fwspec.param[1] = hwirq + priv->parent_irq_base - 32; |
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parent_fwspec.param[2] = fwspec->param[1]; |
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} else if (is_fwnode_irqchip(parent_fwspec.fwnode)) { |
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parent_fwspec.param_count = 2; |
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parent_fwspec.param[0] = hwirq + priv->parent_irq_base; |
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parent_fwspec.param[1] = fwspec->param[1]; |
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} else |
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return -EINVAL; |
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return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, |
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&parent_fwspec); |
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} |
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static const struct irq_domain_ops xgene_gpio_sb_domain_ops = { |
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.translate = xgene_gpio_sb_domain_translate, |
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.alloc = xgene_gpio_sb_domain_alloc, |
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.free = irq_domain_free_irqs_common, |
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.activate = xgene_gpio_sb_domain_activate, |
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.deactivate = xgene_gpio_sb_domain_deactivate, |
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}; |
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static int xgene_gpio_sb_probe(struct platform_device *pdev) |
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{ |
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struct xgene_gpio_sb *priv; |
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int ret; |
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void __iomem *regs; |
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struct irq_domain *parent_domain = NULL; |
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u32 val32; |
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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regs = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(regs)) |
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return PTR_ERR(regs); |
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priv->regs = regs; |
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ret = platform_get_irq(pdev, 0); |
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if (ret > 0) { |
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priv->parent_irq_base = irq_get_irq_data(ret)->hwirq; |
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parent_domain = irq_get_irq_data(ret)->domain; |
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} |
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if (!parent_domain) { |
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dev_err(&pdev->dev, "unable to obtain parent domain\n"); |
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return -ENODEV; |
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} |
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ret = bgpio_init(&priv->gc, &pdev->dev, 4, |
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regs + MPA_GPIO_IN_ADDR, |
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regs + MPA_GPIO_OUT_ADDR, NULL, |
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regs + MPA_GPIO_OE_ADDR, NULL, 0); |
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if (ret) |
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return ret; |
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priv->gc.to_irq = xgene_gpio_sb_to_irq; |
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/* Retrieve start irq pin, use default if property not found */ |
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priv->irq_start = XGENE_DFLT_IRQ_START_PIN; |
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if (!device_property_read_u32(&pdev->dev, |
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XGENE_IRQ_START_PROPERTY, &val32)) |
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priv->irq_start = val32; |
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/* Retrieve number irqs, use default if property not found */ |
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priv->nirq = XGENE_DFLT_MAX_NIRQ; |
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if (!device_property_read_u32(&pdev->dev, XGENE_NIRQ_PROPERTY, &val32)) |
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priv->nirq = val32; |
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/* Retrieve number gpio, use default if property not found */ |
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priv->gc.ngpio = XGENE_DFLT_MAX_NGPIO; |
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if (!device_property_read_u32(&pdev->dev, XGENE_NGPIO_PROPERTY, &val32)) |
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priv->gc.ngpio = val32; |
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dev_info(&pdev->dev, "Support %d gpios, %d irqs start from pin %d\n", |
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priv->gc.ngpio, priv->nirq, priv->irq_start); |
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platform_set_drvdata(pdev, priv); |
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priv->irq_domain = irq_domain_create_hierarchy(parent_domain, |
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0, priv->nirq, pdev->dev.fwnode, |
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&xgene_gpio_sb_domain_ops, priv); |
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if (!priv->irq_domain) |
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return -ENODEV; |
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priv->gc.irq.domain = priv->irq_domain; |
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ret = devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv); |
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if (ret) { |
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dev_err(&pdev->dev, |
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"failed to register X-Gene GPIO Standby driver\n"); |
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irq_domain_remove(priv->irq_domain); |
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return ret; |
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} |
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dev_info(&pdev->dev, "X-Gene GPIO Standby driver registered\n"); |
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/* Register interrupt handlers for GPIO signaled ACPI Events */ |
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acpi_gpiochip_request_interrupts(&priv->gc); |
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return ret; |
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} |
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static int xgene_gpio_sb_remove(struct platform_device *pdev) |
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{ |
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struct xgene_gpio_sb *priv = platform_get_drvdata(pdev); |
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acpi_gpiochip_free_interrupts(&priv->gc); |
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irq_domain_remove(priv->irq_domain); |
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return 0; |
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} |
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static const struct of_device_id xgene_gpio_sb_of_match[] = { |
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{.compatible = "apm,xgene-gpio-sb", }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, xgene_gpio_sb_of_match); |
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#ifdef CONFIG_ACPI |
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static const struct acpi_device_id xgene_gpio_sb_acpi_match[] = { |
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{"APMC0D15", 0}, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(acpi, xgene_gpio_sb_acpi_match); |
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#endif |
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static struct platform_driver xgene_gpio_sb_driver = { |
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.driver = { |
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.name = "xgene-gpio-sb", |
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.of_match_table = xgene_gpio_sb_of_match, |
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.acpi_match_table = ACPI_PTR(xgene_gpio_sb_acpi_match), |
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}, |
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.probe = xgene_gpio_sb_probe, |
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.remove = xgene_gpio_sb_remove, |
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}; |
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module_platform_driver(xgene_gpio_sb_driver); |
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MODULE_AUTHOR("AppliedMicro"); |
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MODULE_DESCRIPTION("APM X-Gene GPIO Standby driver"); |
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MODULE_LICENSE("GPL");
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