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381 lines
9.8 KiB
381 lines
9.8 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* GPIO driver for the ACCES PCI-IDIO-16 |
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* Copyright (C) 2017 William Breathitt Gray |
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*/ |
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#include <linux/bitmap.h> |
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#include <linux/bitops.h> |
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#include <linux/device.h> |
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#include <linux/errno.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/interrupt.h> |
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#include <linux/irqdesc.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/spinlock.h> |
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#include <linux/types.h> |
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/** |
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* struct idio_16_gpio_reg - GPIO device registers structure |
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* @out0_7: Read: FET Drive Outputs 0-7 |
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* Write: FET Drive Outputs 0-7 |
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* @in0_7: Read: Isolated Inputs 0-7 |
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* Write: Clear Interrupt |
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* @irq_ctl: Read: Enable IRQ |
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* Write: Disable IRQ |
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* @filter_ctl: Read: Activate Input Filters 0-15 |
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* Write: Deactivate Input Filters 0-15 |
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* @out8_15: Read: FET Drive Outputs 8-15 |
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* Write: FET Drive Outputs 8-15 |
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* @in8_15: Read: Isolated Inputs 8-15 |
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* Write: Unused |
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* @irq_status: Read: Interrupt status |
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* Write: Unused |
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*/ |
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struct idio_16_gpio_reg { |
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u8 out0_7; |
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u8 in0_7; |
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u8 irq_ctl; |
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u8 filter_ctl; |
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u8 out8_15; |
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u8 in8_15; |
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u8 irq_status; |
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}; |
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/** |
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* struct idio_16_gpio - GPIO device private data structure |
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* @chip: instance of the gpio_chip |
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* @lock: synchronization lock to prevent I/O race conditions |
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* @reg: I/O address offset for the GPIO device registers |
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* @irq_mask: I/O bits affected by interrupts |
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*/ |
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struct idio_16_gpio { |
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struct gpio_chip chip; |
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raw_spinlock_t lock; |
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struct idio_16_gpio_reg __iomem *reg; |
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unsigned long irq_mask; |
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}; |
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static int idio_16_gpio_get_direction(struct gpio_chip *chip, |
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unsigned int offset) |
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{ |
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if (offset > 15) |
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return GPIO_LINE_DIRECTION_IN; |
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return GPIO_LINE_DIRECTION_OUT; |
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} |
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static int idio_16_gpio_direction_input(struct gpio_chip *chip, |
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unsigned int offset) |
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{ |
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return 0; |
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} |
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static int idio_16_gpio_direction_output(struct gpio_chip *chip, |
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unsigned int offset, int value) |
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{ |
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chip->set(chip, offset, value); |
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return 0; |
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} |
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static int idio_16_gpio_get(struct gpio_chip *chip, unsigned int offset) |
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{ |
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struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip); |
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unsigned long mask = BIT(offset); |
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if (offset < 8) |
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return !!(ioread8(&idio16gpio->reg->out0_7) & mask); |
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if (offset < 16) |
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return !!(ioread8(&idio16gpio->reg->out8_15) & (mask >> 8)); |
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if (offset < 24) |
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return !!(ioread8(&idio16gpio->reg->in0_7) & (mask >> 16)); |
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return !!(ioread8(&idio16gpio->reg->in8_15) & (mask >> 24)); |
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} |
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static int idio_16_gpio_get_multiple(struct gpio_chip *chip, |
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unsigned long *mask, unsigned long *bits) |
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{ |
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struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip); |
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unsigned long offset; |
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unsigned long gpio_mask; |
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void __iomem *ports[] = { |
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&idio16gpio->reg->out0_7, &idio16gpio->reg->out8_15, |
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&idio16gpio->reg->in0_7, &idio16gpio->reg->in8_15, |
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}; |
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void __iomem *port_addr; |
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unsigned long port_state; |
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/* clear bits array to a clean slate */ |
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bitmap_zero(bits, chip->ngpio); |
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for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { |
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port_addr = ports[offset / 8]; |
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port_state = ioread8(port_addr) & gpio_mask; |
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bitmap_set_value8(bits, port_state, offset); |
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} |
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return 0; |
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} |
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static void idio_16_gpio_set(struct gpio_chip *chip, unsigned int offset, |
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int value) |
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{ |
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struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip); |
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unsigned int mask = BIT(offset); |
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void __iomem *base; |
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unsigned long flags; |
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unsigned int out_state; |
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if (offset > 15) |
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return; |
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if (offset > 7) { |
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mask >>= 8; |
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base = &idio16gpio->reg->out8_15; |
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} else |
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base = &idio16gpio->reg->out0_7; |
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raw_spin_lock_irqsave(&idio16gpio->lock, flags); |
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if (value) |
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out_state = ioread8(base) | mask; |
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else |
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out_state = ioread8(base) & ~mask; |
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iowrite8(out_state, base); |
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raw_spin_unlock_irqrestore(&idio16gpio->lock, flags); |
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} |
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static void idio_16_gpio_set_multiple(struct gpio_chip *chip, |
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unsigned long *mask, unsigned long *bits) |
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{ |
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struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip); |
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unsigned long offset; |
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unsigned long gpio_mask; |
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void __iomem *ports[] = { |
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&idio16gpio->reg->out0_7, &idio16gpio->reg->out8_15, |
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}; |
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size_t index; |
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void __iomem *port_addr; |
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unsigned long bitmask; |
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unsigned long flags; |
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unsigned long out_state; |
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for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { |
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index = offset / 8; |
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port_addr = ports[index]; |
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bitmask = bitmap_get_value8(bits, offset) & gpio_mask; |
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raw_spin_lock_irqsave(&idio16gpio->lock, flags); |
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out_state = ioread8(port_addr) & ~gpio_mask; |
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out_state |= bitmask; |
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iowrite8(out_state, port_addr); |
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raw_spin_unlock_irqrestore(&idio16gpio->lock, flags); |
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} |
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} |
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static void idio_16_irq_ack(struct irq_data *data) |
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{ |
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} |
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static void idio_16_irq_mask(struct irq_data *data) |
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{ |
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data); |
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struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip); |
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const unsigned long mask = BIT(irqd_to_hwirq(data)); |
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unsigned long flags; |
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idio16gpio->irq_mask &= ~mask; |
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if (!idio16gpio->irq_mask) { |
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raw_spin_lock_irqsave(&idio16gpio->lock, flags); |
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iowrite8(0, &idio16gpio->reg->irq_ctl); |
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raw_spin_unlock_irqrestore(&idio16gpio->lock, flags); |
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} |
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} |
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static void idio_16_irq_unmask(struct irq_data *data) |
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{ |
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data); |
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struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip); |
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const unsigned long mask = BIT(irqd_to_hwirq(data)); |
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const unsigned long prev_irq_mask = idio16gpio->irq_mask; |
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unsigned long flags; |
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idio16gpio->irq_mask |= mask; |
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if (!prev_irq_mask) { |
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raw_spin_lock_irqsave(&idio16gpio->lock, flags); |
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ioread8(&idio16gpio->reg->irq_ctl); |
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raw_spin_unlock_irqrestore(&idio16gpio->lock, flags); |
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} |
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} |
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static int idio_16_irq_set_type(struct irq_data *data, unsigned int flow_type) |
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{ |
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/* The only valid irq types are none and both-edges */ |
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if (flow_type != IRQ_TYPE_NONE && |
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(flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH) |
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return -EINVAL; |
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return 0; |
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} |
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static struct irq_chip idio_16_irqchip = { |
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.name = "pci-idio-16", |
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.irq_ack = idio_16_irq_ack, |
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.irq_mask = idio_16_irq_mask, |
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.irq_unmask = idio_16_irq_unmask, |
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.irq_set_type = idio_16_irq_set_type |
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}; |
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static irqreturn_t idio_16_irq_handler(int irq, void *dev_id) |
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{ |
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struct idio_16_gpio *const idio16gpio = dev_id; |
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unsigned int irq_status; |
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struct gpio_chip *const chip = &idio16gpio->chip; |
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int gpio; |
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raw_spin_lock(&idio16gpio->lock); |
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irq_status = ioread8(&idio16gpio->reg->irq_status); |
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raw_spin_unlock(&idio16gpio->lock); |
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/* Make sure our device generated IRQ */ |
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if (!(irq_status & 0x3) || !(irq_status & 0x4)) |
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return IRQ_NONE; |
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for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio) |
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generic_handle_irq(irq_find_mapping(chip->irq.domain, gpio)); |
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raw_spin_lock(&idio16gpio->lock); |
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/* Clear interrupt */ |
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iowrite8(0, &idio16gpio->reg->in0_7); |
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raw_spin_unlock(&idio16gpio->lock); |
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return IRQ_HANDLED; |
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} |
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#define IDIO_16_NGPIO 32 |
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static const char *idio_16_names[IDIO_16_NGPIO] = { |
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"OUT0", "OUT1", "OUT2", "OUT3", "OUT4", "OUT5", "OUT6", "OUT7", |
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"OUT8", "OUT9", "OUT10", "OUT11", "OUT12", "OUT13", "OUT14", "OUT15", |
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"IIN0", "IIN1", "IIN2", "IIN3", "IIN4", "IIN5", "IIN6", "IIN7", |
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"IIN8", "IIN9", "IIN10", "IIN11", "IIN12", "IIN13", "IIN14", "IIN15" |
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}; |
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static int idio_16_irq_init_hw(struct gpio_chip *gc) |
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{ |
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struct idio_16_gpio *const idio16gpio = gpiochip_get_data(gc); |
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/* Disable IRQ by default and clear any pending interrupt */ |
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iowrite8(0, &idio16gpio->reg->irq_ctl); |
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iowrite8(0, &idio16gpio->reg->in0_7); |
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return 0; |
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} |
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static int idio_16_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
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{ |
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struct device *const dev = &pdev->dev; |
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struct idio_16_gpio *idio16gpio; |
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int err; |
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const size_t pci_bar_index = 2; |
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const char *const name = pci_name(pdev); |
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struct gpio_irq_chip *girq; |
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idio16gpio = devm_kzalloc(dev, sizeof(*idio16gpio), GFP_KERNEL); |
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if (!idio16gpio) |
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return -ENOMEM; |
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err = pcim_enable_device(pdev); |
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if (err) { |
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dev_err(dev, "Failed to enable PCI device (%d)\n", err); |
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return err; |
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} |
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err = pcim_iomap_regions(pdev, BIT(pci_bar_index), name); |
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if (err) { |
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dev_err(dev, "Unable to map PCI I/O addresses (%d)\n", err); |
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return err; |
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} |
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idio16gpio->reg = pcim_iomap_table(pdev)[pci_bar_index]; |
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/* Deactivate input filters */ |
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iowrite8(0, &idio16gpio->reg->filter_ctl); |
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idio16gpio->chip.label = name; |
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idio16gpio->chip.parent = dev; |
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idio16gpio->chip.owner = THIS_MODULE; |
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idio16gpio->chip.base = -1; |
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idio16gpio->chip.ngpio = IDIO_16_NGPIO; |
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idio16gpio->chip.names = idio_16_names; |
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idio16gpio->chip.get_direction = idio_16_gpio_get_direction; |
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idio16gpio->chip.direction_input = idio_16_gpio_direction_input; |
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idio16gpio->chip.direction_output = idio_16_gpio_direction_output; |
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idio16gpio->chip.get = idio_16_gpio_get; |
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idio16gpio->chip.get_multiple = idio_16_gpio_get_multiple; |
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idio16gpio->chip.set = idio_16_gpio_set; |
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idio16gpio->chip.set_multiple = idio_16_gpio_set_multiple; |
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girq = &idio16gpio->chip.irq; |
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girq->chip = &idio_16_irqchip; |
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/* This will let us handle the parent IRQ in the driver */ |
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girq->parent_handler = NULL; |
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girq->num_parents = 0; |
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girq->parents = NULL; |
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girq->default_type = IRQ_TYPE_NONE; |
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girq->handler = handle_edge_irq; |
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girq->init_hw = idio_16_irq_init_hw; |
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raw_spin_lock_init(&idio16gpio->lock); |
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err = devm_gpiochip_add_data(dev, &idio16gpio->chip, idio16gpio); |
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if (err) { |
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dev_err(dev, "GPIO registering failed (%d)\n", err); |
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return err; |
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} |
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err = devm_request_irq(dev, pdev->irq, idio_16_irq_handler, IRQF_SHARED, |
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name, idio16gpio); |
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if (err) { |
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dev_err(dev, "IRQ handler registering failed (%d)\n", err); |
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return err; |
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} |
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return 0; |
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} |
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static const struct pci_device_id idio_16_pci_dev_id[] = { |
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{ PCI_DEVICE(0x494F, 0x0DC8) }, { 0 } |
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}; |
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MODULE_DEVICE_TABLE(pci, idio_16_pci_dev_id); |
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static struct pci_driver idio_16_driver = { |
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.name = "pci-idio-16", |
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.id_table = idio_16_pci_dev_id, |
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.probe = idio_16_probe |
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}; |
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module_pci_driver(idio_16_driver); |
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MODULE_AUTHOR("William Breathitt Gray <[email protected]>"); |
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MODULE_DESCRIPTION("ACCES PCI-IDIO-16 GPIO driver"); |
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MODULE_LICENSE("GPL v2");
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