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597 lines
14 KiB
597 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. |
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*/ |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/slab.h> |
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#include <linux/pci.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#define IOH_EDGE_FALLING 0 |
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#define IOH_EDGE_RISING BIT(0) |
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#define IOH_LEVEL_L BIT(1) |
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#define IOH_LEVEL_H (BIT(0) | BIT(1)) |
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#define IOH_EDGE_BOTH BIT(2) |
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#define IOH_IM_MASK (BIT(0) | BIT(1) | BIT(2)) |
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#define IOH_IRQ_BASE 0 |
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struct ioh_reg_comn { |
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u32 ien; |
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u32 istatus; |
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u32 idisp; |
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u32 iclr; |
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u32 imask; |
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u32 imaskclr; |
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u32 po; |
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u32 pi; |
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u32 pm; |
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u32 im_0; |
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u32 im_1; |
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u32 reserved; |
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}; |
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struct ioh_regs { |
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struct ioh_reg_comn regs[8]; |
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u32 reserve1[16]; |
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u32 ioh_sel_reg[4]; |
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u32 reserve2[11]; |
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u32 srst; |
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}; |
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/** |
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* struct ioh_gpio_reg_data - The register store data. |
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* @ien_reg: To store contents of interrupt enable register. |
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* @imask_reg: To store contents of interrupt mask regist |
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* @po_reg: To store contents of PO register. |
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* @pm_reg: To store contents of PM register. |
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* @im0_reg: To store contents of interrupt mode regist0 |
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* @im1_reg: To store contents of interrupt mode regist1 |
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* @use_sel_reg: To store contents of GPIO_USE_SEL0~3 |
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*/ |
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struct ioh_gpio_reg_data { |
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u32 ien_reg; |
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u32 imask_reg; |
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u32 po_reg; |
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u32 pm_reg; |
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u32 im0_reg; |
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u32 im1_reg; |
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u32 use_sel_reg; |
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}; |
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/** |
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* struct ioh_gpio - GPIO private data structure. |
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* @base: PCI base address of Memory mapped I/O register. |
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* @reg: Memory mapped IOH GPIO register list. |
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* @dev: Pointer to device structure. |
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* @gpio: Data for GPIO infrastructure. |
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* @ioh_gpio_reg: Memory mapped Register data is saved here |
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* when suspend. |
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* @gpio_use_sel: Save GPIO_USE_SEL1~4 register for PM |
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* @ch: Indicate GPIO channel |
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* @irq_base: Save base of IRQ number for interrupt |
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* @spinlock: Used for register access protection |
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*/ |
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struct ioh_gpio { |
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void __iomem *base; |
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struct ioh_regs __iomem *reg; |
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struct device *dev; |
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struct gpio_chip gpio; |
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struct ioh_gpio_reg_data ioh_gpio_reg; |
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u32 gpio_use_sel; |
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int ch; |
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int irq_base; |
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spinlock_t spinlock; |
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}; |
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static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12}; |
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static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val) |
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{ |
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u32 reg_val; |
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struct ioh_gpio *chip = gpiochip_get_data(gpio); |
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unsigned long flags; |
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spin_lock_irqsave(&chip->spinlock, flags); |
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reg_val = ioread32(&chip->reg->regs[chip->ch].po); |
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if (val) |
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reg_val |= (1 << nr); |
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else |
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reg_val &= ~(1 << nr); |
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iowrite32(reg_val, &chip->reg->regs[chip->ch].po); |
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spin_unlock_irqrestore(&chip->spinlock, flags); |
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} |
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static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr) |
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{ |
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struct ioh_gpio *chip = gpiochip_get_data(gpio); |
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return !!(ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr)); |
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} |
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static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr, |
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int val) |
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{ |
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struct ioh_gpio *chip = gpiochip_get_data(gpio); |
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u32 pm; |
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u32 reg_val; |
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unsigned long flags; |
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spin_lock_irqsave(&chip->spinlock, flags); |
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pm = ioread32(&chip->reg->regs[chip->ch].pm) & |
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((1 << num_ports[chip->ch]) - 1); |
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pm |= (1 << nr); |
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iowrite32(pm, &chip->reg->regs[chip->ch].pm); |
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reg_val = ioread32(&chip->reg->regs[chip->ch].po); |
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if (val) |
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reg_val |= (1 << nr); |
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else |
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reg_val &= ~(1 << nr); |
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iowrite32(reg_val, &chip->reg->regs[chip->ch].po); |
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spin_unlock_irqrestore(&chip->spinlock, flags); |
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return 0; |
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} |
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static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) |
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{ |
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struct ioh_gpio *chip = gpiochip_get_data(gpio); |
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u32 pm; |
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unsigned long flags; |
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spin_lock_irqsave(&chip->spinlock, flags); |
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pm = ioread32(&chip->reg->regs[chip->ch].pm) & |
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((1 << num_ports[chip->ch]) - 1); |
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pm &= ~(1 << nr); |
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iowrite32(pm, &chip->reg->regs[chip->ch].pm); |
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spin_unlock_irqrestore(&chip->spinlock, flags); |
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return 0; |
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} |
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#ifdef CONFIG_PM |
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/* |
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* Save register configuration and disable interrupts. |
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*/ |
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static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip) |
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{ |
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int i; |
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for (i = 0; i < 8; i ++, chip++) { |
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chip->ioh_gpio_reg.po_reg = |
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ioread32(&chip->reg->regs[chip->ch].po); |
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chip->ioh_gpio_reg.pm_reg = |
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ioread32(&chip->reg->regs[chip->ch].pm); |
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chip->ioh_gpio_reg.ien_reg = |
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ioread32(&chip->reg->regs[chip->ch].ien); |
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chip->ioh_gpio_reg.imask_reg = |
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ioread32(&chip->reg->regs[chip->ch].imask); |
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chip->ioh_gpio_reg.im0_reg = |
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ioread32(&chip->reg->regs[chip->ch].im_0); |
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chip->ioh_gpio_reg.im1_reg = |
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ioread32(&chip->reg->regs[chip->ch].im_1); |
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if (i < 4) |
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chip->ioh_gpio_reg.use_sel_reg = |
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ioread32(&chip->reg->ioh_sel_reg[i]); |
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} |
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} |
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/* |
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* This function restores the register configuration of the GPIO device. |
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*/ |
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static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip) |
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{ |
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int i; |
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for (i = 0; i < 8; i ++, chip++) { |
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iowrite32(chip->ioh_gpio_reg.po_reg, |
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&chip->reg->regs[chip->ch].po); |
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iowrite32(chip->ioh_gpio_reg.pm_reg, |
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&chip->reg->regs[chip->ch].pm); |
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iowrite32(chip->ioh_gpio_reg.ien_reg, |
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&chip->reg->regs[chip->ch].ien); |
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iowrite32(chip->ioh_gpio_reg.imask_reg, |
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&chip->reg->regs[chip->ch].imask); |
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iowrite32(chip->ioh_gpio_reg.im0_reg, |
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&chip->reg->regs[chip->ch].im_0); |
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iowrite32(chip->ioh_gpio_reg.im1_reg, |
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&chip->reg->regs[chip->ch].im_1); |
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if (i < 4) |
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iowrite32(chip->ioh_gpio_reg.use_sel_reg, |
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&chip->reg->ioh_sel_reg[i]); |
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} |
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} |
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#endif |
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static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset) |
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{ |
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struct ioh_gpio *chip = gpiochip_get_data(gpio); |
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return chip->irq_base + offset; |
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} |
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static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port) |
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{ |
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struct gpio_chip *gpio = &chip->gpio; |
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gpio->label = dev_name(chip->dev); |
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gpio->owner = THIS_MODULE; |
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gpio->direction_input = ioh_gpio_direction_input; |
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gpio->get = ioh_gpio_get; |
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gpio->direction_output = ioh_gpio_direction_output; |
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gpio->set = ioh_gpio_set; |
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gpio->dbg_show = NULL; |
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gpio->base = -1; |
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gpio->ngpio = num_port; |
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gpio->can_sleep = false; |
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gpio->to_irq = ioh_gpio_to_irq; |
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} |
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static int ioh_irq_type(struct irq_data *d, unsigned int type) |
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{ |
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u32 im; |
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void __iomem *im_reg; |
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u32 ien; |
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u32 im_pos; |
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int ch; |
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unsigned long flags; |
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u32 val; |
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int irq = d->irq; |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct ioh_gpio *chip = gc->private; |
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ch = irq - chip->irq_base; |
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if (irq <= chip->irq_base + 7) { |
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im_reg = &chip->reg->regs[chip->ch].im_0; |
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im_pos = ch; |
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} else { |
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im_reg = &chip->reg->regs[chip->ch].im_1; |
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im_pos = ch - 8; |
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} |
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dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n", |
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__func__, irq, type, ch, im_pos, type); |
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spin_lock_irqsave(&chip->spinlock, flags); |
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switch (type) { |
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case IRQ_TYPE_EDGE_RISING: |
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val = IOH_EDGE_RISING; |
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break; |
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case IRQ_TYPE_EDGE_FALLING: |
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val = IOH_EDGE_FALLING; |
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break; |
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case IRQ_TYPE_EDGE_BOTH: |
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val = IOH_EDGE_BOTH; |
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break; |
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case IRQ_TYPE_LEVEL_HIGH: |
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val = IOH_LEVEL_H; |
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break; |
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case IRQ_TYPE_LEVEL_LOW: |
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val = IOH_LEVEL_L; |
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break; |
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case IRQ_TYPE_PROBE: |
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goto end; |
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default: |
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dev_warn(chip->dev, "%s: unknown type(%dd)", |
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__func__, type); |
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goto end; |
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} |
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/* Set interrupt mode */ |
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im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4)); |
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iowrite32(im | (val << (im_pos * 4)), im_reg); |
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/* iclr */ |
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iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr); |
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/* IMASKCLR */ |
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iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr); |
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/* Enable interrupt */ |
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ien = ioread32(&chip->reg->regs[chip->ch].ien); |
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iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien); |
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end: |
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spin_unlock_irqrestore(&chip->spinlock, flags); |
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return 0; |
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} |
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static void ioh_irq_unmask(struct irq_data *d) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct ioh_gpio *chip = gc->private; |
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iowrite32(1 << (d->irq - chip->irq_base), |
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&chip->reg->regs[chip->ch].imaskclr); |
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} |
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static void ioh_irq_mask(struct irq_data *d) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct ioh_gpio *chip = gc->private; |
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iowrite32(1 << (d->irq - chip->irq_base), |
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&chip->reg->regs[chip->ch].imask); |
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} |
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static void ioh_irq_disable(struct irq_data *d) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct ioh_gpio *chip = gc->private; |
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unsigned long flags; |
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u32 ien; |
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spin_lock_irqsave(&chip->spinlock, flags); |
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ien = ioread32(&chip->reg->regs[chip->ch].ien); |
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ien &= ~(1 << (d->irq - chip->irq_base)); |
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iowrite32(ien, &chip->reg->regs[chip->ch].ien); |
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spin_unlock_irqrestore(&chip->spinlock, flags); |
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} |
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static void ioh_irq_enable(struct irq_data *d) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct ioh_gpio *chip = gc->private; |
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unsigned long flags; |
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u32 ien; |
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spin_lock_irqsave(&chip->spinlock, flags); |
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ien = ioread32(&chip->reg->regs[chip->ch].ien); |
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ien |= 1 << (d->irq - chip->irq_base); |
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iowrite32(ien, &chip->reg->regs[chip->ch].ien); |
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spin_unlock_irqrestore(&chip->spinlock, flags); |
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} |
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static irqreturn_t ioh_gpio_handler(int irq, void *dev_id) |
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{ |
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struct ioh_gpio *chip = dev_id; |
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u32 reg_val; |
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int i, j; |
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int ret = IRQ_NONE; |
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for (i = 0; i < 8; i++, chip++) { |
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reg_val = ioread32(&chip->reg->regs[i].istatus); |
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for (j = 0; j < num_ports[i]; j++) { |
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if (reg_val & BIT(j)) { |
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dev_dbg(chip->dev, |
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"%s:[%d]:irq=%d status=0x%x\n", |
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__func__, j, irq, reg_val); |
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iowrite32(BIT(j), |
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&chip->reg->regs[chip->ch].iclr); |
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generic_handle_irq(chip->irq_base + j); |
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ret = IRQ_HANDLED; |
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} |
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} |
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} |
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return ret; |
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} |
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static int ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip, |
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unsigned int irq_start, |
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unsigned int num) |
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{ |
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struct irq_chip_generic *gc; |
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struct irq_chip_type *ct; |
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int rv; |
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gc = devm_irq_alloc_generic_chip(chip->dev, "ioh_gpio", 1, irq_start, |
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chip->base, handle_simple_irq); |
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if (!gc) |
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return -ENOMEM; |
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gc->private = chip; |
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ct = gc->chip_types; |
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ct->chip.irq_mask = ioh_irq_mask; |
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ct->chip.irq_unmask = ioh_irq_unmask; |
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ct->chip.irq_set_type = ioh_irq_type; |
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ct->chip.irq_disable = ioh_irq_disable; |
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ct->chip.irq_enable = ioh_irq_enable; |
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rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num), |
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IRQ_GC_INIT_MASK_CACHE, |
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IRQ_NOREQUEST | IRQ_NOPROBE, 0); |
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return rv; |
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} |
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static int ioh_gpio_probe(struct pci_dev *pdev, |
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const struct pci_device_id *id) |
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{ |
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int ret; |
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int i, j; |
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struct ioh_gpio *chip; |
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void __iomem *base; |
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void *chip_save; |
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int irq_base; |
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ret = pci_enable_device(pdev); |
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if (ret) { |
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dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__); |
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goto err_pci_enable; |
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} |
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ret = pci_request_regions(pdev, KBUILD_MODNAME); |
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if (ret) { |
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dev_err(&pdev->dev, "pci_request_regions failed-%d", ret); |
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goto err_request_regions; |
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} |
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base = pci_iomap(pdev, 1, 0); |
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if (!base) { |
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dev_err(&pdev->dev, "%s : pci_iomap failed", __func__); |
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ret = -ENOMEM; |
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goto err_iomap; |
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} |
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chip_save = kcalloc(8, sizeof(*chip), GFP_KERNEL); |
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if (chip_save == NULL) { |
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ret = -ENOMEM; |
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goto err_kzalloc; |
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} |
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chip = chip_save; |
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for (i = 0; i < 8; i++, chip++) { |
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chip->dev = &pdev->dev; |
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chip->base = base; |
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chip->reg = chip->base; |
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chip->ch = i; |
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spin_lock_init(&chip->spinlock); |
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ioh_gpio_setup(chip, num_ports[i]); |
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ret = gpiochip_add_data(&chip->gpio, chip); |
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if (ret) { |
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dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n"); |
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goto err_gpiochip_add; |
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} |
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} |
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chip = chip_save; |
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for (j = 0; j < 8; j++, chip++) { |
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irq_base = devm_irq_alloc_descs(&pdev->dev, -1, IOH_IRQ_BASE, |
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num_ports[j], NUMA_NO_NODE); |
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if (irq_base < 0) { |
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dev_warn(&pdev->dev, |
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"ml_ioh_gpio: Failed to get IRQ base num\n"); |
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ret = irq_base; |
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goto err_gpiochip_add; |
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} |
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chip->irq_base = irq_base; |
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ret = ioh_gpio_alloc_generic_chip(chip, |
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irq_base, num_ports[j]); |
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if (ret) |
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goto err_gpiochip_add; |
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} |
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chip = chip_save; |
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ret = devm_request_irq(&pdev->dev, pdev->irq, ioh_gpio_handler, |
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IRQF_SHARED, KBUILD_MODNAME, chip); |
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if (ret != 0) { |
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dev_err(&pdev->dev, |
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"%s request_irq failed\n", __func__); |
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goto err_gpiochip_add; |
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} |
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pci_set_drvdata(pdev, chip); |
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return 0; |
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err_gpiochip_add: |
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chip = chip_save; |
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while (--i >= 0) { |
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gpiochip_remove(&chip->gpio); |
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chip++; |
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} |
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kfree(chip_save); |
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err_kzalloc: |
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pci_iounmap(pdev, base); |
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err_iomap: |
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pci_release_regions(pdev); |
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err_request_regions: |
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pci_disable_device(pdev); |
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err_pci_enable: |
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dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret); |
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return ret; |
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} |
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static void ioh_gpio_remove(struct pci_dev *pdev) |
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{ |
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int i; |
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struct ioh_gpio *chip = pci_get_drvdata(pdev); |
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void *chip_save; |
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chip_save = chip; |
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for (i = 0; i < 8; i++, chip++) |
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gpiochip_remove(&chip->gpio); |
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chip = chip_save; |
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pci_iounmap(pdev, chip->base); |
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pci_release_regions(pdev); |
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pci_disable_device(pdev); |
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kfree(chip); |
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} |
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#ifdef CONFIG_PM |
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static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state) |
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{ |
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s32 ret; |
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struct ioh_gpio *chip = pci_get_drvdata(pdev); |
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unsigned long flags; |
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spin_lock_irqsave(&chip->spinlock, flags); |
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ioh_gpio_save_reg_conf(chip); |
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spin_unlock_irqrestore(&chip->spinlock, flags); |
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ret = pci_save_state(pdev); |
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if (ret) { |
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dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret); |
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return ret; |
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} |
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pci_disable_device(pdev); |
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pci_set_power_state(pdev, PCI_D0); |
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ret = pci_enable_wake(pdev, PCI_D0, 1); |
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if (ret) |
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dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret); |
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return 0; |
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} |
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static int ioh_gpio_resume(struct pci_dev *pdev) |
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{ |
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s32 ret; |
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struct ioh_gpio *chip = pci_get_drvdata(pdev); |
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unsigned long flags; |
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ret = pci_enable_wake(pdev, PCI_D0, 0); |
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|
|
pci_set_power_state(pdev, PCI_D0); |
|
ret = pci_enable_device(pdev); |
|
if (ret) { |
|
dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret); |
|
return ret; |
|
} |
|
pci_restore_state(pdev); |
|
|
|
spin_lock_irqsave(&chip->spinlock, flags); |
|
iowrite32(0x01, &chip->reg->srst); |
|
iowrite32(0x00, &chip->reg->srst); |
|
ioh_gpio_restore_reg_conf(chip); |
|
spin_unlock_irqrestore(&chip->spinlock, flags); |
|
|
|
return 0; |
|
} |
|
#else |
|
#define ioh_gpio_suspend NULL |
|
#define ioh_gpio_resume NULL |
|
#endif |
|
|
|
static const struct pci_device_id ioh_gpio_pcidev_id[] = { |
|
{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) }, |
|
{ 0, } |
|
}; |
|
MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id); |
|
|
|
static struct pci_driver ioh_gpio_driver = { |
|
.name = "ml_ioh_gpio", |
|
.id_table = ioh_gpio_pcidev_id, |
|
.probe = ioh_gpio_probe, |
|
.remove = ioh_gpio_remove, |
|
.suspend = ioh_gpio_suspend, |
|
.resume = ioh_gpio_resume |
|
}; |
|
|
|
module_pci_driver(ioh_gpio_driver); |
|
|
|
MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver"); |
|
MODULE_LICENSE("GPL");
|
|
|