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525 lines
13 KiB
525 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Intel Merrifield SoC GPIO driver |
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* |
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* Copyright (c) 2016 Intel Corporation. |
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* Author: Andy Shevchenko <[email protected]> |
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*/ |
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#include <linux/acpi.h> |
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#include <linux/bitops.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/pinctrl/consumer.h> |
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#define GCCR 0x000 /* controller configuration */ |
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#define GPLR 0x004 /* pin level r/o */ |
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#define GPDR 0x01c /* pin direction */ |
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#define GPSR 0x034 /* pin set w/o */ |
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#define GPCR 0x04c /* pin clear w/o */ |
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#define GRER 0x064 /* rising edge detect */ |
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#define GFER 0x07c /* falling edge detect */ |
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#define GFBR 0x094 /* glitch filter bypass */ |
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#define GIMR 0x0ac /* interrupt mask */ |
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#define GISR 0x0c4 /* interrupt source */ |
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#define GITR 0x300 /* input type */ |
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#define GLPR 0x318 /* level input polarity */ |
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#define GWMR 0x400 /* wake mask */ |
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#define GWSR 0x418 /* wake source */ |
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#define GSIR 0xc00 /* secure input */ |
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/* Intel Merrifield has 192 GPIO pins */ |
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#define MRFLD_NGPIO 192 |
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struct mrfld_gpio_pinrange { |
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unsigned int gpio_base; |
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unsigned int pin_base; |
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unsigned int npins; |
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}; |
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#define GPIO_PINRANGE(gstart, gend, pstart) \ |
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{ \ |
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.gpio_base = (gstart), \ |
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.pin_base = (pstart), \ |
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.npins = (gend) - (gstart) + 1, \ |
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} |
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struct mrfld_gpio { |
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struct gpio_chip chip; |
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void __iomem *reg_base; |
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raw_spinlock_t lock; |
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struct device *dev; |
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}; |
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static const struct mrfld_gpio_pinrange mrfld_gpio_ranges[] = { |
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GPIO_PINRANGE(0, 11, 146), |
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GPIO_PINRANGE(12, 13, 144), |
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GPIO_PINRANGE(14, 15, 35), |
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GPIO_PINRANGE(16, 16, 164), |
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GPIO_PINRANGE(17, 18, 105), |
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GPIO_PINRANGE(19, 22, 101), |
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GPIO_PINRANGE(23, 30, 107), |
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GPIO_PINRANGE(32, 43, 67), |
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GPIO_PINRANGE(44, 63, 195), |
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GPIO_PINRANGE(64, 67, 140), |
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GPIO_PINRANGE(68, 69, 165), |
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GPIO_PINRANGE(70, 71, 65), |
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GPIO_PINRANGE(72, 76, 228), |
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GPIO_PINRANGE(77, 86, 37), |
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GPIO_PINRANGE(87, 87, 48), |
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GPIO_PINRANGE(88, 88, 47), |
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GPIO_PINRANGE(89, 96, 49), |
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GPIO_PINRANGE(97, 97, 34), |
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GPIO_PINRANGE(102, 119, 83), |
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GPIO_PINRANGE(120, 123, 79), |
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GPIO_PINRANGE(124, 135, 115), |
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GPIO_PINRANGE(137, 142, 158), |
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GPIO_PINRANGE(154, 163, 24), |
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GPIO_PINRANGE(164, 176, 215), |
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GPIO_PINRANGE(177, 189, 127), |
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GPIO_PINRANGE(190, 191, 178), |
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}; |
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static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset, |
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unsigned int reg_type_offset) |
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{ |
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struct mrfld_gpio *priv = gpiochip_get_data(chip); |
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u8 reg = offset / 32; |
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return priv->reg_base + reg_type_offset + reg * 4; |
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} |
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static int mrfld_gpio_get(struct gpio_chip *chip, unsigned int offset) |
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{ |
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void __iomem *gplr = gpio_reg(chip, offset, GPLR); |
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return !!(readl(gplr) & BIT(offset % 32)); |
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} |
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static void mrfld_gpio_set(struct gpio_chip *chip, unsigned int offset, |
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int value) |
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{ |
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struct mrfld_gpio *priv = gpiochip_get_data(chip); |
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void __iomem *gpsr, *gpcr; |
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unsigned long flags; |
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raw_spin_lock_irqsave(&priv->lock, flags); |
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if (value) { |
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gpsr = gpio_reg(chip, offset, GPSR); |
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writel(BIT(offset % 32), gpsr); |
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} else { |
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gpcr = gpio_reg(chip, offset, GPCR); |
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writel(BIT(offset % 32), gpcr); |
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} |
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raw_spin_unlock_irqrestore(&priv->lock, flags); |
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} |
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static int mrfld_gpio_direction_input(struct gpio_chip *chip, |
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unsigned int offset) |
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{ |
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struct mrfld_gpio *priv = gpiochip_get_data(chip); |
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void __iomem *gpdr = gpio_reg(chip, offset, GPDR); |
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unsigned long flags; |
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u32 value; |
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raw_spin_lock_irqsave(&priv->lock, flags); |
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value = readl(gpdr); |
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value &= ~BIT(offset % 32); |
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writel(value, gpdr); |
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raw_spin_unlock_irqrestore(&priv->lock, flags); |
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return 0; |
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} |
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static int mrfld_gpio_direction_output(struct gpio_chip *chip, |
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unsigned int offset, int value) |
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{ |
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struct mrfld_gpio *priv = gpiochip_get_data(chip); |
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void __iomem *gpdr = gpio_reg(chip, offset, GPDR); |
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unsigned long flags; |
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mrfld_gpio_set(chip, offset, value); |
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raw_spin_lock_irqsave(&priv->lock, flags); |
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value = readl(gpdr); |
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value |= BIT(offset % 32); |
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writel(value, gpdr); |
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raw_spin_unlock_irqrestore(&priv->lock, flags); |
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return 0; |
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} |
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static int mrfld_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) |
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{ |
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void __iomem *gpdr = gpio_reg(chip, offset, GPDR); |
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if (readl(gpdr) & BIT(offset % 32)) |
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return GPIO_LINE_DIRECTION_OUT; |
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return GPIO_LINE_DIRECTION_IN; |
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} |
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static int mrfld_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset, |
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unsigned int debounce) |
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{ |
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struct mrfld_gpio *priv = gpiochip_get_data(chip); |
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void __iomem *gfbr = gpio_reg(chip, offset, GFBR); |
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unsigned long flags; |
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u32 value; |
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raw_spin_lock_irqsave(&priv->lock, flags); |
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if (debounce) |
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value = readl(gfbr) & ~BIT(offset % 32); |
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else |
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value = readl(gfbr) | BIT(offset % 32); |
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writel(value, gfbr); |
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raw_spin_unlock_irqrestore(&priv->lock, flags); |
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return 0; |
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} |
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static int mrfld_gpio_set_config(struct gpio_chip *chip, unsigned int offset, |
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unsigned long config) |
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{ |
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u32 debounce; |
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if ((pinconf_to_config_param(config) == PIN_CONFIG_BIAS_DISABLE) || |
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(pinconf_to_config_param(config) == PIN_CONFIG_BIAS_PULL_UP) || |
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(pinconf_to_config_param(config) == PIN_CONFIG_BIAS_PULL_DOWN)) |
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return gpiochip_generic_config(chip, offset, config); |
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if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) |
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return -ENOTSUPP; |
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debounce = pinconf_to_config_argument(config); |
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return mrfld_gpio_set_debounce(chip, offset, debounce); |
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} |
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static void mrfld_irq_ack(struct irq_data *d) |
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{ |
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struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d); |
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u32 gpio = irqd_to_hwirq(d); |
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void __iomem *gisr = gpio_reg(&priv->chip, gpio, GISR); |
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unsigned long flags; |
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raw_spin_lock_irqsave(&priv->lock, flags); |
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writel(BIT(gpio % 32), gisr); |
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raw_spin_unlock_irqrestore(&priv->lock, flags); |
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} |
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static void mrfld_irq_unmask_mask(struct irq_data *d, bool unmask) |
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{ |
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struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d); |
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u32 gpio = irqd_to_hwirq(d); |
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void __iomem *gimr = gpio_reg(&priv->chip, gpio, GIMR); |
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unsigned long flags; |
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u32 value; |
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raw_spin_lock_irqsave(&priv->lock, flags); |
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if (unmask) |
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value = readl(gimr) | BIT(gpio % 32); |
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else |
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value = readl(gimr) & ~BIT(gpio % 32); |
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writel(value, gimr); |
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raw_spin_unlock_irqrestore(&priv->lock, flags); |
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} |
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static void mrfld_irq_mask(struct irq_data *d) |
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{ |
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mrfld_irq_unmask_mask(d, false); |
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} |
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static void mrfld_irq_unmask(struct irq_data *d) |
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{ |
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mrfld_irq_unmask_mask(d, true); |
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} |
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static int mrfld_irq_set_type(struct irq_data *d, unsigned int type) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct mrfld_gpio *priv = gpiochip_get_data(gc); |
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u32 gpio = irqd_to_hwirq(d); |
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void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER); |
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void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER); |
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void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR); |
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void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR); |
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unsigned long flags; |
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u32 value; |
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raw_spin_lock_irqsave(&priv->lock, flags); |
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if (type & IRQ_TYPE_EDGE_RISING) |
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value = readl(grer) | BIT(gpio % 32); |
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else |
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value = readl(grer) & ~BIT(gpio % 32); |
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writel(value, grer); |
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if (type & IRQ_TYPE_EDGE_FALLING) |
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value = readl(gfer) | BIT(gpio % 32); |
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else |
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value = readl(gfer) & ~BIT(gpio % 32); |
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writel(value, gfer); |
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/* |
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* To prevent glitches from triggering an unintended level interrupt, |
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* configure GLPR register first and then configure GITR. |
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*/ |
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if (type & IRQ_TYPE_LEVEL_LOW) |
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value = readl(glpr) | BIT(gpio % 32); |
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else |
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value = readl(glpr) & ~BIT(gpio % 32); |
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writel(value, glpr); |
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if (type & IRQ_TYPE_LEVEL_MASK) { |
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value = readl(gitr) | BIT(gpio % 32); |
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writel(value, gitr); |
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irq_set_handler_locked(d, handle_level_irq); |
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} else if (type & IRQ_TYPE_EDGE_BOTH) { |
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value = readl(gitr) & ~BIT(gpio % 32); |
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writel(value, gitr); |
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irq_set_handler_locked(d, handle_edge_irq); |
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} |
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raw_spin_unlock_irqrestore(&priv->lock, flags); |
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return 0; |
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} |
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static int mrfld_irq_set_wake(struct irq_data *d, unsigned int on) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct mrfld_gpio *priv = gpiochip_get_data(gc); |
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u32 gpio = irqd_to_hwirq(d); |
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void __iomem *gwmr = gpio_reg(&priv->chip, gpio, GWMR); |
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void __iomem *gwsr = gpio_reg(&priv->chip, gpio, GWSR); |
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unsigned long flags; |
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u32 value; |
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raw_spin_lock_irqsave(&priv->lock, flags); |
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/* Clear the existing wake status */ |
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writel(BIT(gpio % 32), gwsr); |
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if (on) |
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value = readl(gwmr) | BIT(gpio % 32); |
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else |
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value = readl(gwmr) & ~BIT(gpio % 32); |
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writel(value, gwmr); |
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raw_spin_unlock_irqrestore(&priv->lock, flags); |
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dev_dbg(priv->dev, "%sable wake for gpio %u\n", on ? "en" : "dis", gpio); |
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return 0; |
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} |
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static struct irq_chip mrfld_irqchip = { |
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.name = "gpio-merrifield", |
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.irq_ack = mrfld_irq_ack, |
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.irq_mask = mrfld_irq_mask, |
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.irq_unmask = mrfld_irq_unmask, |
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.irq_set_type = mrfld_irq_set_type, |
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.irq_set_wake = mrfld_irq_set_wake, |
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}; |
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static void mrfld_irq_handler(struct irq_desc *desc) |
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{ |
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struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
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struct mrfld_gpio *priv = gpiochip_get_data(gc); |
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struct irq_chip *irqchip = irq_desc_get_chip(desc); |
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unsigned long base, gpio; |
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chained_irq_enter(irqchip, desc); |
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/* Check GPIO controller to check which pin triggered the interrupt */ |
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for (base = 0; base < priv->chip.ngpio; base += 32) { |
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void __iomem *gisr = gpio_reg(&priv->chip, base, GISR); |
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void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR); |
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unsigned long pending, enabled; |
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pending = readl(gisr); |
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enabled = readl(gimr); |
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/* Only interrupts that are enabled */ |
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pending &= enabled; |
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for_each_set_bit(gpio, &pending, 32) { |
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unsigned int irq; |
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irq = irq_find_mapping(gc->irq.domain, base + gpio); |
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generic_handle_irq(irq); |
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} |
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} |
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chained_irq_exit(irqchip, desc); |
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} |
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static int mrfld_irq_init_hw(struct gpio_chip *chip) |
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{ |
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struct mrfld_gpio *priv = gpiochip_get_data(chip); |
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void __iomem *reg; |
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unsigned int base; |
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for (base = 0; base < priv->chip.ngpio; base += 32) { |
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/* Clear the rising-edge detect register */ |
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reg = gpio_reg(&priv->chip, base, GRER); |
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writel(0, reg); |
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/* Clear the falling-edge detect register */ |
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reg = gpio_reg(&priv->chip, base, GFER); |
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writel(0, reg); |
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} |
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return 0; |
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} |
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static const char *mrfld_gpio_get_pinctrl_dev_name(struct mrfld_gpio *priv) |
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{ |
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struct acpi_device *adev; |
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const char *name; |
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adev = acpi_dev_get_first_match_dev("INTC1002", NULL, -1); |
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if (adev) { |
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name = devm_kstrdup(priv->dev, acpi_dev_name(adev), GFP_KERNEL); |
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acpi_dev_put(adev); |
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} else { |
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name = "pinctrl-merrifield"; |
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} |
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return name; |
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} |
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static int mrfld_gpio_add_pin_ranges(struct gpio_chip *chip) |
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{ |
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struct mrfld_gpio *priv = gpiochip_get_data(chip); |
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const struct mrfld_gpio_pinrange *range; |
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const char *pinctrl_dev_name; |
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unsigned int i; |
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int retval; |
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pinctrl_dev_name = mrfld_gpio_get_pinctrl_dev_name(priv); |
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for (i = 0; i < ARRAY_SIZE(mrfld_gpio_ranges); i++) { |
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range = &mrfld_gpio_ranges[i]; |
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retval = gpiochip_add_pin_range(&priv->chip, pinctrl_dev_name, |
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range->gpio_base, |
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range->pin_base, |
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range->npins); |
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if (retval) { |
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dev_err(priv->dev, "failed to add GPIO pin range\n"); |
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return retval; |
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} |
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} |
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return 0; |
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} |
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static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
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{ |
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struct gpio_irq_chip *girq; |
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struct mrfld_gpio *priv; |
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u32 gpio_base, irq_base; |
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void __iomem *base; |
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int retval; |
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retval = pcim_enable_device(pdev); |
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if (retval) |
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return retval; |
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retval = pcim_iomap_regions(pdev, BIT(1) | BIT(0), pci_name(pdev)); |
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if (retval) { |
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dev_err(&pdev->dev, "I/O memory mapping error\n"); |
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return retval; |
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} |
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base = pcim_iomap_table(pdev)[1]; |
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irq_base = readl(base + 0 * sizeof(u32)); |
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gpio_base = readl(base + 1 * sizeof(u32)); |
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/* Release the IO mapping, since we already get the info from BAR1 */ |
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pcim_iounmap_regions(pdev, BIT(1)); |
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->dev = &pdev->dev; |
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priv->reg_base = pcim_iomap_table(pdev)[0]; |
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priv->chip.label = dev_name(&pdev->dev); |
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priv->chip.parent = &pdev->dev; |
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priv->chip.request = gpiochip_generic_request; |
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priv->chip.free = gpiochip_generic_free; |
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priv->chip.direction_input = mrfld_gpio_direction_input; |
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priv->chip.direction_output = mrfld_gpio_direction_output; |
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priv->chip.get = mrfld_gpio_get; |
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priv->chip.set = mrfld_gpio_set; |
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priv->chip.get_direction = mrfld_gpio_get_direction; |
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priv->chip.set_config = mrfld_gpio_set_config; |
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priv->chip.base = gpio_base; |
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priv->chip.ngpio = MRFLD_NGPIO; |
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priv->chip.can_sleep = false; |
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priv->chip.add_pin_ranges = mrfld_gpio_add_pin_ranges; |
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raw_spin_lock_init(&priv->lock); |
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retval = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
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if (retval < 0) |
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return retval; |
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girq = &priv->chip.irq; |
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girq->chip = &mrfld_irqchip; |
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girq->init_hw = mrfld_irq_init_hw; |
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girq->parent_handler = mrfld_irq_handler; |
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girq->num_parents = 1; |
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girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents, |
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sizeof(*girq->parents), GFP_KERNEL); |
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if (!girq->parents) |
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return -ENOMEM; |
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girq->parents[0] = pci_irq_vector(pdev, 0); |
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girq->first = irq_base; |
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girq->default_type = IRQ_TYPE_NONE; |
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girq->handler = handle_bad_irq; |
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retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv); |
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if (retval) { |
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dev_err(&pdev->dev, "gpiochip_add error %d\n", retval); |
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return retval; |
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} |
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pci_set_drvdata(pdev, priv); |
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return 0; |
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} |
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static const struct pci_device_id mrfld_gpio_ids[] = { |
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{ PCI_VDEVICE(INTEL, 0x1199) }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(pci, mrfld_gpio_ids); |
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static struct pci_driver mrfld_gpio_driver = { |
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.name = "gpio-merrifield", |
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.id_table = mrfld_gpio_ids, |
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.probe = mrfld_gpio_probe, |
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}; |
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module_pci_driver(mrfld_gpio_driver); |
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MODULE_AUTHOR("Andy Shevchenko <[email protected]>"); |
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MODULE_DESCRIPTION("Intel Merrifield SoC GPIO driver"); |
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MODULE_LICENSE("GPL v2");
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