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546 lines
12 KiB
546 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2011-2012 Avionic Design GmbH |
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*/ |
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#include <linux/gpio/driver.h> |
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#include <linux/i2c.h> |
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#include <linux/interrupt.h> |
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#include <linux/module.h> |
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#include <linux/of_irq.h> |
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#include <linux/seq_file.h> |
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#include <linux/slab.h> |
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#define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift) |
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#define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift) |
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#define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift) |
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#define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift) |
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#define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift) |
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struct adnp { |
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struct i2c_client *client; |
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struct gpio_chip gpio; |
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unsigned int reg_shift; |
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struct mutex i2c_lock; |
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struct mutex irq_lock; |
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u8 *irq_enable; |
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u8 *irq_level; |
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u8 *irq_rise; |
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u8 *irq_fall; |
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u8 *irq_high; |
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u8 *irq_low; |
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}; |
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static int adnp_read(struct adnp *adnp, unsigned offset, uint8_t *value) |
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{ |
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int err; |
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err = i2c_smbus_read_byte_data(adnp->client, offset); |
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if (err < 0) { |
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dev_err(adnp->gpio.parent, "%s failed: %d\n", |
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"i2c_smbus_read_byte_data()", err); |
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return err; |
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} |
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*value = err; |
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return 0; |
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} |
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static int adnp_write(struct adnp *adnp, unsigned offset, uint8_t value) |
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{ |
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int err; |
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err = i2c_smbus_write_byte_data(adnp->client, offset, value); |
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if (err < 0) { |
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dev_err(adnp->gpio.parent, "%s failed: %d\n", |
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"i2c_smbus_write_byte_data()", err); |
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return err; |
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} |
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return 0; |
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} |
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static int adnp_gpio_get(struct gpio_chip *chip, unsigned offset) |
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{ |
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struct adnp *adnp = gpiochip_get_data(chip); |
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unsigned int reg = offset >> adnp->reg_shift; |
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unsigned int pos = offset & 7; |
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u8 value; |
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int err; |
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err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &value); |
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if (err < 0) |
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return err; |
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return (value & BIT(pos)) ? 1 : 0; |
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} |
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static void __adnp_gpio_set(struct adnp *adnp, unsigned offset, int value) |
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{ |
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unsigned int reg = offset >> adnp->reg_shift; |
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unsigned int pos = offset & 7; |
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int err; |
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u8 val; |
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err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val); |
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if (err < 0) |
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return; |
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if (value) |
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val |= BIT(pos); |
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else |
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val &= ~BIT(pos); |
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adnp_write(adnp, GPIO_PLR(adnp) + reg, val); |
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} |
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static void adnp_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
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{ |
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struct adnp *adnp = gpiochip_get_data(chip); |
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mutex_lock(&adnp->i2c_lock); |
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__adnp_gpio_set(adnp, offset, value); |
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mutex_unlock(&adnp->i2c_lock); |
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} |
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static int adnp_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
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{ |
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struct adnp *adnp = gpiochip_get_data(chip); |
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unsigned int reg = offset >> adnp->reg_shift; |
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unsigned int pos = offset & 7; |
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u8 value; |
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int err; |
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mutex_lock(&adnp->i2c_lock); |
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err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value); |
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if (err < 0) |
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goto out; |
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value &= ~BIT(pos); |
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err = adnp_write(adnp, GPIO_DDR(adnp) + reg, value); |
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if (err < 0) |
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goto out; |
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err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value); |
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if (err < 0) |
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goto out; |
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if (value & BIT(pos)) { |
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err = -EPERM; |
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goto out; |
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} |
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err = 0; |
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out: |
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mutex_unlock(&adnp->i2c_lock); |
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return err; |
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} |
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static int adnp_gpio_direction_output(struct gpio_chip *chip, unsigned offset, |
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int value) |
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{ |
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struct adnp *adnp = gpiochip_get_data(chip); |
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unsigned int reg = offset >> adnp->reg_shift; |
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unsigned int pos = offset & 7; |
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int err; |
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u8 val; |
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mutex_lock(&adnp->i2c_lock); |
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err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val); |
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if (err < 0) |
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goto out; |
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val |= BIT(pos); |
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err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val); |
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if (err < 0) |
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goto out; |
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err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val); |
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if (err < 0) |
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goto out; |
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if (!(val & BIT(pos))) { |
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err = -EPERM; |
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goto out; |
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} |
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__adnp_gpio_set(adnp, offset, value); |
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err = 0; |
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out: |
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mutex_unlock(&adnp->i2c_lock); |
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return err; |
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} |
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static void adnp_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) |
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{ |
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struct adnp *adnp = gpiochip_get_data(chip); |
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unsigned int num_regs = 1 << adnp->reg_shift, i, j; |
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int err; |
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for (i = 0; i < num_regs; i++) { |
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u8 ddr, plr, ier, isr; |
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mutex_lock(&adnp->i2c_lock); |
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err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr); |
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if (err < 0) |
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goto unlock; |
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err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr); |
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if (err < 0) |
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goto unlock; |
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err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier); |
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if (err < 0) |
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goto unlock; |
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err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr); |
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if (err < 0) |
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goto unlock; |
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mutex_unlock(&adnp->i2c_lock); |
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for (j = 0; j < 8; j++) { |
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unsigned int bit = (i << adnp->reg_shift) + j; |
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const char *direction = "input "; |
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const char *level = "low "; |
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const char *interrupt = "disabled"; |
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const char *pending = ""; |
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if (ddr & BIT(j)) |
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direction = "output"; |
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if (plr & BIT(j)) |
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level = "high"; |
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if (ier & BIT(j)) |
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interrupt = "enabled "; |
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if (isr & BIT(j)) |
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pending = "pending"; |
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seq_printf(s, "%2u: %s %s IRQ %s %s\n", bit, |
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direction, level, interrupt, pending); |
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} |
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} |
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return; |
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unlock: |
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mutex_unlock(&adnp->i2c_lock); |
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} |
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static irqreturn_t adnp_irq(int irq, void *data) |
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{ |
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struct adnp *adnp = data; |
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unsigned int num_regs, i; |
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num_regs = 1 << adnp->reg_shift; |
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for (i = 0; i < num_regs; i++) { |
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unsigned int base = i << adnp->reg_shift, bit; |
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u8 changed, level, isr, ier; |
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unsigned long pending; |
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int err; |
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mutex_lock(&adnp->i2c_lock); |
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err = adnp_read(adnp, GPIO_PLR(adnp) + i, &level); |
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if (err < 0) { |
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mutex_unlock(&adnp->i2c_lock); |
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continue; |
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} |
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err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr); |
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if (err < 0) { |
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mutex_unlock(&adnp->i2c_lock); |
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continue; |
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} |
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err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier); |
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if (err < 0) { |
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mutex_unlock(&adnp->i2c_lock); |
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continue; |
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} |
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mutex_unlock(&adnp->i2c_lock); |
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/* determine pins that changed levels */ |
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changed = level ^ adnp->irq_level[i]; |
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/* compute edge-triggered interrupts */ |
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pending = changed & ((adnp->irq_fall[i] & ~level) | |
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(adnp->irq_rise[i] & level)); |
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/* add in level-triggered interrupts */ |
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pending |= (adnp->irq_high[i] & level) | |
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(adnp->irq_low[i] & ~level); |
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/* mask out non-pending and disabled interrupts */ |
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pending &= isr & ier; |
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for_each_set_bit(bit, &pending, 8) { |
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unsigned int child_irq; |
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child_irq = irq_find_mapping(adnp->gpio.irq.domain, |
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base + bit); |
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handle_nested_irq(child_irq); |
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} |
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} |
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return IRQ_HANDLED; |
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} |
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static void adnp_irq_mask(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct adnp *adnp = gpiochip_get_data(gc); |
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unsigned int reg = d->hwirq >> adnp->reg_shift; |
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unsigned int pos = d->hwirq & 7; |
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adnp->irq_enable[reg] &= ~BIT(pos); |
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} |
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static void adnp_irq_unmask(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct adnp *adnp = gpiochip_get_data(gc); |
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unsigned int reg = d->hwirq >> adnp->reg_shift; |
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unsigned int pos = d->hwirq & 7; |
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adnp->irq_enable[reg] |= BIT(pos); |
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} |
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static int adnp_irq_set_type(struct irq_data *d, unsigned int type) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct adnp *adnp = gpiochip_get_data(gc); |
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unsigned int reg = d->hwirq >> adnp->reg_shift; |
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unsigned int pos = d->hwirq & 7; |
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if (type & IRQ_TYPE_EDGE_RISING) |
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adnp->irq_rise[reg] |= BIT(pos); |
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else |
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adnp->irq_rise[reg] &= ~BIT(pos); |
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if (type & IRQ_TYPE_EDGE_FALLING) |
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adnp->irq_fall[reg] |= BIT(pos); |
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else |
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adnp->irq_fall[reg] &= ~BIT(pos); |
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if (type & IRQ_TYPE_LEVEL_HIGH) |
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adnp->irq_high[reg] |= BIT(pos); |
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else |
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adnp->irq_high[reg] &= ~BIT(pos); |
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if (type & IRQ_TYPE_LEVEL_LOW) |
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adnp->irq_low[reg] |= BIT(pos); |
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else |
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adnp->irq_low[reg] &= ~BIT(pos); |
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return 0; |
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} |
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static void adnp_irq_bus_lock(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct adnp *adnp = gpiochip_get_data(gc); |
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mutex_lock(&adnp->irq_lock); |
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} |
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static void adnp_irq_bus_unlock(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct adnp *adnp = gpiochip_get_data(gc); |
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unsigned int num_regs = 1 << adnp->reg_shift, i; |
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mutex_lock(&adnp->i2c_lock); |
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for (i = 0; i < num_regs; i++) |
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adnp_write(adnp, GPIO_IER(adnp) + i, adnp->irq_enable[i]); |
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mutex_unlock(&adnp->i2c_lock); |
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mutex_unlock(&adnp->irq_lock); |
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} |
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static struct irq_chip adnp_irq_chip = { |
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.name = "gpio-adnp", |
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.irq_mask = adnp_irq_mask, |
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.irq_unmask = adnp_irq_unmask, |
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.irq_set_type = adnp_irq_set_type, |
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.irq_bus_lock = adnp_irq_bus_lock, |
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.irq_bus_sync_unlock = adnp_irq_bus_unlock, |
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}; |
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static int adnp_irq_setup(struct adnp *adnp) |
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{ |
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unsigned int num_regs = 1 << adnp->reg_shift, i; |
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struct gpio_chip *chip = &adnp->gpio; |
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int err; |
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mutex_init(&adnp->irq_lock); |
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/* |
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* Allocate memory to keep track of the current level and trigger |
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* modes of the interrupts. To avoid multiple allocations, a single |
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* large buffer is allocated and pointers are setup to point at the |
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* corresponding offsets. For consistency, the layout of the buffer |
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* is chosen to match the register layout of the hardware in that |
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* each segment contains the corresponding bits for all interrupts. |
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*/ |
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adnp->irq_enable = devm_kcalloc(chip->parent, num_regs, 6, |
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GFP_KERNEL); |
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if (!adnp->irq_enable) |
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return -ENOMEM; |
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adnp->irq_level = adnp->irq_enable + (num_regs * 1); |
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adnp->irq_rise = adnp->irq_enable + (num_regs * 2); |
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adnp->irq_fall = adnp->irq_enable + (num_regs * 3); |
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adnp->irq_high = adnp->irq_enable + (num_regs * 4); |
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adnp->irq_low = adnp->irq_enable + (num_regs * 5); |
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for (i = 0; i < num_regs; i++) { |
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/* |
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* Read the initial level of all pins to allow the emulation |
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* of edge triggered interrupts. |
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*/ |
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err = adnp_read(adnp, GPIO_PLR(adnp) + i, &adnp->irq_level[i]); |
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if (err < 0) |
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return err; |
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/* disable all interrupts */ |
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err = adnp_write(adnp, GPIO_IER(adnp) + i, 0); |
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if (err < 0) |
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return err; |
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adnp->irq_enable[i] = 0x00; |
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} |
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err = devm_request_threaded_irq(chip->parent, adnp->client->irq, |
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NULL, adnp_irq, |
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IRQF_TRIGGER_RISING | IRQF_ONESHOT, |
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dev_name(chip->parent), adnp); |
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if (err != 0) { |
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dev_err(chip->parent, "can't request IRQ#%d: %d\n", |
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adnp->client->irq, err); |
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return err; |
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} |
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return 0; |
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} |
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static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios, |
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bool is_irq_controller) |
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{ |
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struct gpio_chip *chip = &adnp->gpio; |
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int err; |
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adnp->reg_shift = get_count_order(num_gpios) - 3; |
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chip->direction_input = adnp_gpio_direction_input; |
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chip->direction_output = adnp_gpio_direction_output; |
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chip->get = adnp_gpio_get; |
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chip->set = adnp_gpio_set; |
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chip->can_sleep = true; |
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if (IS_ENABLED(CONFIG_DEBUG_FS)) |
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chip->dbg_show = adnp_gpio_dbg_show; |
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chip->base = -1; |
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chip->ngpio = num_gpios; |
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chip->label = adnp->client->name; |
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chip->parent = &adnp->client->dev; |
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chip->of_node = chip->parent->of_node; |
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chip->owner = THIS_MODULE; |
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if (is_irq_controller) { |
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struct gpio_irq_chip *girq; |
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err = adnp_irq_setup(adnp); |
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if (err) |
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return err; |
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girq = &chip->irq; |
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girq->chip = &adnp_irq_chip; |
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/* This will let us handle the parent IRQ in the driver */ |
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girq->parent_handler = NULL; |
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girq->num_parents = 0; |
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girq->parents = NULL; |
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girq->default_type = IRQ_TYPE_NONE; |
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girq->handler = handle_simple_irq; |
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girq->threaded = true; |
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} |
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err = devm_gpiochip_add_data(&adnp->client->dev, chip, adnp); |
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if (err) |
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return err; |
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return 0; |
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} |
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static int adnp_i2c_probe(struct i2c_client *client, |
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const struct i2c_device_id *id) |
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{ |
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struct device_node *np = client->dev.of_node; |
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struct adnp *adnp; |
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u32 num_gpios; |
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int err; |
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err = of_property_read_u32(np, "nr-gpios", &num_gpios); |
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if (err < 0) |
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return err; |
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client->irq = irq_of_parse_and_map(np, 0); |
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if (!client->irq) |
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return -EPROBE_DEFER; |
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adnp = devm_kzalloc(&client->dev, sizeof(*adnp), GFP_KERNEL); |
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if (!adnp) |
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return -ENOMEM; |
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mutex_init(&adnp->i2c_lock); |
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adnp->client = client; |
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err = adnp_gpio_setup(adnp, num_gpios, |
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of_property_read_bool(np, "interrupt-controller")); |
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if (err) |
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return err; |
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i2c_set_clientdata(client, adnp); |
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return 0; |
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} |
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static const struct i2c_device_id adnp_i2c_id[] = { |
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{ "gpio-adnp" }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(i2c, adnp_i2c_id); |
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static const struct of_device_id adnp_of_match[] = { |
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{ .compatible = "ad,gpio-adnp", }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, adnp_of_match); |
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static struct i2c_driver adnp_i2c_driver = { |
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.driver = { |
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.name = "gpio-adnp", |
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.of_match_table = adnp_of_match, |
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}, |
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.probe = adnp_i2c_probe, |
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.id_table = adnp_i2c_id, |
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}; |
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module_i2c_driver(adnp_i2c_driver); |
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MODULE_DESCRIPTION("Avionic Design N-bit GPIO expander"); |
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MODULE_AUTHOR("Thierry Reding <[email protected]>"); |
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MODULE_LICENSE("GPL");
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