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588 lines
18 KiB
588 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* DFL device driver for Nios private feature on Intel PAC (Programmable |
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* Acceleration Card) N3000 |
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* |
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* Copyright (C) 2019-2020 Intel Corporation, Inc. |
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* |
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* Authors: |
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* Wu Hao <[email protected]> |
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* Xu Yilun <[email protected]> |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/dfl.h> |
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#include <linux/errno.h> |
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#include <linux/io.h> |
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#include <linux/io-64-nonatomic-lo-hi.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <linux/stddef.h> |
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#include <linux/spi/altera.h> |
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#include <linux/spi/spi.h> |
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#include <linux/types.h> |
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/* |
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* N3000 Nios private feature registers, named as NIOS_SPI_XX on spec. |
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* NS is the abbreviation of NIOS_SPI. |
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*/ |
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#define N3000_NS_PARAM 0x8 |
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#define N3000_NS_PARAM_SHIFT_MODE_MSK BIT_ULL(1) |
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#define N3000_NS_PARAM_SHIFT_MODE_MSB 0 |
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#define N3000_NS_PARAM_SHIFT_MODE_LSB 1 |
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#define N3000_NS_PARAM_DATA_WIDTH GENMASK_ULL(7, 2) |
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#define N3000_NS_PARAM_NUM_CS GENMASK_ULL(13, 8) |
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#define N3000_NS_PARAM_CLK_POL BIT_ULL(14) |
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#define N3000_NS_PARAM_CLK_PHASE BIT_ULL(15) |
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#define N3000_NS_PARAM_PERIPHERAL_ID GENMASK_ULL(47, 32) |
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#define N3000_NS_CTRL 0x10 |
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#define N3000_NS_CTRL_WR_DATA GENMASK_ULL(31, 0) |
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#define N3000_NS_CTRL_ADDR GENMASK_ULL(44, 32) |
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#define N3000_NS_CTRL_CMD_MSK GENMASK_ULL(63, 62) |
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#define N3000_NS_CTRL_CMD_NOP 0 |
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#define N3000_NS_CTRL_CMD_RD 1 |
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#define N3000_NS_CTRL_CMD_WR 2 |
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#define N3000_NS_STAT 0x18 |
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#define N3000_NS_STAT_RD_DATA GENMASK_ULL(31, 0) |
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#define N3000_NS_STAT_RW_VAL BIT_ULL(32) |
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/* Nios handshake registers, indirect access */ |
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#define N3000_NIOS_INIT 0x1000 |
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#define N3000_NIOS_INIT_DONE BIT(0) |
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#define N3000_NIOS_INIT_START BIT(1) |
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/* Mode for retimer A, link 0, the same below */ |
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#define N3000_NIOS_INIT_REQ_FEC_MODE_A0_MSK GENMASK(9, 8) |
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#define N3000_NIOS_INIT_REQ_FEC_MODE_A1_MSK GENMASK(11, 10) |
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#define N3000_NIOS_INIT_REQ_FEC_MODE_A2_MSK GENMASK(13, 12) |
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#define N3000_NIOS_INIT_REQ_FEC_MODE_A3_MSK GENMASK(15, 14) |
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#define N3000_NIOS_INIT_REQ_FEC_MODE_B0_MSK GENMASK(17, 16) |
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#define N3000_NIOS_INIT_REQ_FEC_MODE_B1_MSK GENMASK(19, 18) |
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#define N3000_NIOS_INIT_REQ_FEC_MODE_B2_MSK GENMASK(21, 20) |
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#define N3000_NIOS_INIT_REQ_FEC_MODE_B3_MSK GENMASK(23, 22) |
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#define N3000_NIOS_INIT_REQ_FEC_MODE_NO 0x0 |
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#define N3000_NIOS_INIT_REQ_FEC_MODE_KR 0x1 |
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#define N3000_NIOS_INIT_REQ_FEC_MODE_RS 0x2 |
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#define N3000_NIOS_FW_VERSION 0x1004 |
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#define N3000_NIOS_FW_VERSION_PATCH GENMASK(23, 20) |
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#define N3000_NIOS_FW_VERSION_MINOR GENMASK(27, 24) |
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#define N3000_NIOS_FW_VERSION_MAJOR GENMASK(31, 28) |
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/* The retimers we use on Intel PAC N3000 is Parkvale, abbreviated to PKVL */ |
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#define N3000_NIOS_PKVL_A_MODE_STS 0x1020 |
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#define N3000_NIOS_PKVL_B_MODE_STS 0x1024 |
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#define N3000_NIOS_PKVL_MODE_STS_GROUP_MSK GENMASK(15, 8) |
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#define N3000_NIOS_PKVL_MODE_STS_GROUP_OK 0x0 |
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#define N3000_NIOS_PKVL_MODE_STS_ID_MSK GENMASK(7, 0) |
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/* When GROUP MASK field == GROUP_OK */ |
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#define N3000_NIOS_PKVL_MODE_ID_RESET 0x0 |
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#define N3000_NIOS_PKVL_MODE_ID_4X10G 0x1 |
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#define N3000_NIOS_PKVL_MODE_ID_4X25G 0x2 |
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#define N3000_NIOS_PKVL_MODE_ID_2X25G 0x3 |
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#define N3000_NIOS_PKVL_MODE_ID_2X25G_2X10G 0x4 |
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#define N3000_NIOS_PKVL_MODE_ID_1X25G 0x5 |
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#define N3000_NIOS_REGBUS_RETRY_COUNT 10000 /* loop count */ |
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#define N3000_NIOS_INIT_TIMEOUT 10000000 /* usec */ |
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#define N3000_NIOS_INIT_TIME_INTV 100000 /* usec */ |
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#define N3000_NIOS_INIT_REQ_FEC_MODE_MSK_ALL \ |
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(N3000_NIOS_INIT_REQ_FEC_MODE_A0_MSK | \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_A1_MSK | \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_A2_MSK | \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_A3_MSK | \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_B0_MSK | \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_B1_MSK | \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_B2_MSK | \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_B3_MSK) |
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#define N3000_NIOS_INIT_REQ_FEC_MODE_NO_ALL \ |
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(FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A0_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_NO) | \ |
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FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A1_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_NO) | \ |
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FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A2_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_NO) | \ |
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FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A3_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_NO) | \ |
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FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B0_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_NO) | \ |
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FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B1_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_NO) | \ |
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FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B2_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_NO) | \ |
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FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B3_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_NO)) |
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#define N3000_NIOS_INIT_REQ_FEC_MODE_KR_ALL \ |
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(FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A0_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_KR) | \ |
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FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A1_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_KR) | \ |
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FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A2_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_KR) | \ |
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FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A3_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_KR) | \ |
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FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B0_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_KR) | \ |
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FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B1_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_KR) | \ |
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FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B2_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_KR) | \ |
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FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B3_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_KR)) |
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#define N3000_NIOS_INIT_REQ_FEC_MODE_RS_ALL \ |
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(FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A0_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_RS) | \ |
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FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A1_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_RS) | \ |
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FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A2_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_RS) | \ |
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FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A3_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_RS) | \ |
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FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B0_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_RS) | \ |
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FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B1_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_RS) | \ |
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FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B2_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_RS) | \ |
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FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B3_MSK, \ |
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N3000_NIOS_INIT_REQ_FEC_MODE_RS)) |
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struct n3000_nios { |
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void __iomem *base; |
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struct regmap *regmap; |
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struct device *dev; |
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struct platform_device *altera_spi; |
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}; |
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static ssize_t nios_fw_version_show(struct device *dev, |
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struct device_attribute *attr, char *buf) |
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{ |
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struct n3000_nios *nn = dev_get_drvdata(dev); |
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unsigned int val; |
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int ret; |
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ret = regmap_read(nn->regmap, N3000_NIOS_FW_VERSION, &val); |
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if (ret) |
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return ret; |
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return sysfs_emit(buf, "%x.%x.%x\n", |
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(u8)FIELD_GET(N3000_NIOS_FW_VERSION_MAJOR, val), |
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(u8)FIELD_GET(N3000_NIOS_FW_VERSION_MINOR, val), |
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(u8)FIELD_GET(N3000_NIOS_FW_VERSION_PATCH, val)); |
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} |
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static DEVICE_ATTR_RO(nios_fw_version); |
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#define IS_MODE_STATUS_OK(mode_stat) \ |
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(FIELD_GET(N3000_NIOS_PKVL_MODE_STS_GROUP_MSK, (mode_stat)) == \ |
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N3000_NIOS_PKVL_MODE_STS_GROUP_OK) |
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#define IS_RETIMER_FEC_SUPPORTED(retimer_mode) \ |
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((retimer_mode) != N3000_NIOS_PKVL_MODE_ID_RESET && \ |
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(retimer_mode) != N3000_NIOS_PKVL_MODE_ID_4X10G) |
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static int get_retimer_mode(struct n3000_nios *nn, unsigned int mode_stat_reg, |
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unsigned int *retimer_mode) |
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{ |
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unsigned int val; |
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int ret; |
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ret = regmap_read(nn->regmap, mode_stat_reg, &val); |
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if (ret) |
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return ret; |
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if (!IS_MODE_STATUS_OK(val)) |
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return -EFAULT; |
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*retimer_mode = FIELD_GET(N3000_NIOS_PKVL_MODE_STS_ID_MSK, val); |
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return 0; |
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} |
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static ssize_t retimer_A_mode_show(struct device *dev, |
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struct device_attribute *attr, char *buf) |
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{ |
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struct n3000_nios *nn = dev_get_drvdata(dev); |
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unsigned int mode; |
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int ret; |
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ret = get_retimer_mode(nn, N3000_NIOS_PKVL_A_MODE_STS, &mode); |
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if (ret) |
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return ret; |
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return sysfs_emit(buf, "0x%x\n", mode); |
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} |
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static DEVICE_ATTR_RO(retimer_A_mode); |
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static ssize_t retimer_B_mode_show(struct device *dev, |
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struct device_attribute *attr, char *buf) |
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{ |
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struct n3000_nios *nn = dev_get_drvdata(dev); |
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unsigned int mode; |
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int ret; |
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ret = get_retimer_mode(nn, N3000_NIOS_PKVL_B_MODE_STS, &mode); |
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if (ret) |
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return ret; |
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return sysfs_emit(buf, "0x%x\n", mode); |
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} |
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static DEVICE_ATTR_RO(retimer_B_mode); |
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static ssize_t fec_mode_show(struct device *dev, |
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struct device_attribute *attr, char *buf) |
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{ |
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unsigned int val, retimer_a_mode, retimer_b_mode, fec_modes; |
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struct n3000_nios *nn = dev_get_drvdata(dev); |
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int ret; |
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/* FEC mode setting is not supported in early FW versions */ |
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ret = regmap_read(nn->regmap, N3000_NIOS_FW_VERSION, &val); |
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if (ret) |
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return ret; |
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if (FIELD_GET(N3000_NIOS_FW_VERSION_MAJOR, val) < 3) |
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return sysfs_emit(buf, "not supported\n"); |
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/* If no 25G links, FEC mode setting is not supported either */ |
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ret = get_retimer_mode(nn, N3000_NIOS_PKVL_A_MODE_STS, &retimer_a_mode); |
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if (ret) |
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return ret; |
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ret = get_retimer_mode(nn, N3000_NIOS_PKVL_B_MODE_STS, &retimer_b_mode); |
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if (ret) |
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return ret; |
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if (!IS_RETIMER_FEC_SUPPORTED(retimer_a_mode) && |
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!IS_RETIMER_FEC_SUPPORTED(retimer_b_mode)) |
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return sysfs_emit(buf, "not supported\n"); |
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/* get the valid FEC mode for 25G links */ |
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ret = regmap_read(nn->regmap, N3000_NIOS_INIT, &val); |
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if (ret) |
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return ret; |
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/* |
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* FEC mode should always be the same for all links, as we set them |
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* in this way. |
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*/ |
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fec_modes = (val & N3000_NIOS_INIT_REQ_FEC_MODE_MSK_ALL); |
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if (fec_modes == N3000_NIOS_INIT_REQ_FEC_MODE_NO_ALL) |
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return sysfs_emit(buf, "no\n"); |
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else if (fec_modes == N3000_NIOS_INIT_REQ_FEC_MODE_KR_ALL) |
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return sysfs_emit(buf, "kr\n"); |
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else if (fec_modes == N3000_NIOS_INIT_REQ_FEC_MODE_RS_ALL) |
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return sysfs_emit(buf, "rs\n"); |
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return -EFAULT; |
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} |
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static DEVICE_ATTR_RO(fec_mode); |
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static struct attribute *n3000_nios_attrs[] = { |
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&dev_attr_nios_fw_version.attr, |
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&dev_attr_retimer_A_mode.attr, |
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&dev_attr_retimer_B_mode.attr, |
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&dev_attr_fec_mode.attr, |
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NULL, |
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}; |
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ATTRIBUTE_GROUPS(n3000_nios); |
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static int n3000_nios_init_done_check(struct n3000_nios *nn) |
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{ |
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unsigned int val, state_a, state_b; |
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struct device *dev = nn->dev; |
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int ret, ret2; |
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/* |
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* The SPI is shared by the Nios core inside the FPGA, Nios will use |
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* this SPI master to do some one time initialization after power up, |
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* and then release the control to OS. The driver needs to poll on |
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* INIT_DONE to see when driver could take the control. |
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* |
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* Please note that after Nios firmware version 3.0.0, INIT_START is |
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* introduced, so driver needs to trigger START firstly and then check |
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* INIT_DONE. |
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*/ |
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ret = regmap_read(nn->regmap, N3000_NIOS_FW_VERSION, &val); |
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if (ret) |
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return ret; |
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/* |
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* If Nios version register is totally uninitialized(== 0x0), then the |
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* Nios firmware is missing. So host could take control of SPI master |
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* safely, but initialization work for Nios is not done. To restore the |
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* card, we need to reprogram a new Nios firmware via the BMC chip on |
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* SPI bus. So the driver doesn't error out, it continues to create the |
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* spi controller device and spi_board_info for BMC. |
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*/ |
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if (val == 0) { |
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dev_err(dev, "Nios version reg = 0x%x, skip INIT_DONE check, but the retimer may be uninitialized\n", |
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val); |
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return 0; |
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} |
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if (FIELD_GET(N3000_NIOS_FW_VERSION_MAJOR, val) >= 3) { |
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/* read NIOS_INIT to check if retimer initialization is done */ |
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ret = regmap_read(nn->regmap, N3000_NIOS_INIT, &val); |
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if (ret) |
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return ret; |
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/* check if retimers are initialized already */ |
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if (val & (N3000_NIOS_INIT_DONE | N3000_NIOS_INIT_START)) |
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goto nios_init_done; |
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/* configure FEC mode per module param */ |
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val = N3000_NIOS_INIT_START; |
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/* |
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* When the retimer is to be set to 10G mode, there is no FEC |
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* mode setting, so the REQ_FEC_MODE field will be ignored by |
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* Nios firmware in this case. But we should still fill the FEC |
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* mode field cause host could not get the retimer working mode |
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* until the Nios init is done. |
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* |
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* For now the driver doesn't support the retimer FEC mode |
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* switching per user's request. It is always set to Reed |
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* Solomon FEC. |
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* |
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* The driver will set the same FEC mode for all links. |
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*/ |
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val |= N3000_NIOS_INIT_REQ_FEC_MODE_RS_ALL; |
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ret = regmap_write(nn->regmap, N3000_NIOS_INIT, val); |
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if (ret) |
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return ret; |
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} |
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nios_init_done: |
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/* polls on NIOS_INIT_DONE */ |
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ret = regmap_read_poll_timeout(nn->regmap, N3000_NIOS_INIT, val, |
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val & N3000_NIOS_INIT_DONE, |
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N3000_NIOS_INIT_TIME_INTV, |
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N3000_NIOS_INIT_TIMEOUT); |
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if (ret) |
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dev_err(dev, "NIOS_INIT_DONE %s\n", |
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(ret == -ETIMEDOUT) ? "timed out" : "check error"); |
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ret2 = regmap_read(nn->regmap, N3000_NIOS_PKVL_A_MODE_STS, &state_a); |
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if (ret2) |
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return ret2; |
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ret2 = regmap_read(nn->regmap, N3000_NIOS_PKVL_B_MODE_STS, &state_b); |
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if (ret2) |
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return ret2; |
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if (!ret) { |
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/* |
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* After INIT_DONE is detected, it still needs to check if the |
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* Nios firmware reports any error during the retimer |
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* configuration. |
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*/ |
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if (IS_MODE_STATUS_OK(state_a) && IS_MODE_STATUS_OK(state_b)) |
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return 0; |
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/* |
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* If the retimer configuration is failed, the Nios firmware |
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* will still release the spi controller for host to |
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* communicate with the BMC. It makes possible for people to |
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* reprogram a new Nios firmware and restore the card. So the |
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* driver doesn't error out, it continues to create the spi |
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* controller device and spi_board_info for BMC. |
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*/ |
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dev_err(dev, "NIOS_INIT_DONE OK, but err on retimer init\n"); |
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} |
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dev_err(nn->dev, "PKVL_A_MODE_STS 0x%x\n", state_a); |
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dev_err(nn->dev, "PKVL_B_MODE_STS 0x%x\n", state_b); |
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return ret; |
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} |
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static struct spi_board_info m10_n3000_info = { |
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.modalias = "m10-n3000", |
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.max_speed_hz = 12500000, |
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.bus_num = 0, |
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.chip_select = 0, |
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}; |
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static int create_altera_spi_controller(struct n3000_nios *nn) |
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{ |
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struct altera_spi_platform_data pdata = { 0 }; |
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struct platform_device_info pdevinfo = { 0 }; |
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void __iomem *base = nn->base; |
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u64 v; |
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v = readq(base + N3000_NS_PARAM); |
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pdata.mode_bits = SPI_CS_HIGH; |
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if (FIELD_GET(N3000_NS_PARAM_CLK_POL, v)) |
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pdata.mode_bits |= SPI_CPOL; |
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if (FIELD_GET(N3000_NS_PARAM_CLK_PHASE, v)) |
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pdata.mode_bits |= SPI_CPHA; |
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pdata.num_chipselect = FIELD_GET(N3000_NS_PARAM_NUM_CS, v); |
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pdata.bits_per_word_mask = |
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SPI_BPW_RANGE_MASK(1, FIELD_GET(N3000_NS_PARAM_DATA_WIDTH, v)); |
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pdata.num_devices = 1; |
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pdata.devices = &m10_n3000_info; |
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dev_dbg(nn->dev, "%s cs %u bpm 0x%x mode 0x%x\n", __func__, |
|
pdata.num_chipselect, pdata.bits_per_word_mask, |
|
pdata.mode_bits); |
|
|
|
pdevinfo.name = "subdev_spi_altera"; |
|
pdevinfo.id = PLATFORM_DEVID_AUTO; |
|
pdevinfo.parent = nn->dev; |
|
pdevinfo.data = &pdata; |
|
pdevinfo.size_data = sizeof(pdata); |
|
|
|
nn->altera_spi = platform_device_register_full(&pdevinfo); |
|
return PTR_ERR_OR_ZERO(nn->altera_spi); |
|
} |
|
|
|
static void destroy_altera_spi_controller(struct n3000_nios *nn) |
|
{ |
|
platform_device_unregister(nn->altera_spi); |
|
} |
|
|
|
static int n3000_nios_poll_stat_timeout(void __iomem *base, u64 *v) |
|
{ |
|
int loops; |
|
|
|
/* |
|
* We don't use the time based timeout here for performance. |
|
* |
|
* The regbus read/write is on the critical path of Intel PAC N3000 |
|
* image programing. The time based timeout checking will add too much |
|
* overhead on it. Usually the state changes in 1 or 2 loops on the |
|
* test server, and we set 10000 times loop here for safety. |
|
*/ |
|
for (loops = N3000_NIOS_REGBUS_RETRY_COUNT; loops > 0 ; loops--) { |
|
*v = readq(base + N3000_NS_STAT); |
|
if (*v & N3000_NS_STAT_RW_VAL) |
|
break; |
|
cpu_relax(); |
|
} |
|
|
|
return (loops > 0) ? 0 : -ETIMEDOUT; |
|
} |
|
|
|
static int n3000_nios_reg_write(void *context, unsigned int reg, unsigned int val) |
|
{ |
|
struct n3000_nios *nn = context; |
|
u64 v; |
|
int ret; |
|
|
|
v = FIELD_PREP(N3000_NS_CTRL_CMD_MSK, N3000_NS_CTRL_CMD_WR) | |
|
FIELD_PREP(N3000_NS_CTRL_ADDR, reg) | |
|
FIELD_PREP(N3000_NS_CTRL_WR_DATA, val); |
|
writeq(v, nn->base + N3000_NS_CTRL); |
|
|
|
ret = n3000_nios_poll_stat_timeout(nn->base, &v); |
|
if (ret) |
|
dev_err(nn->dev, "fail to write reg 0x%x val 0x%x: %d\n", |
|
reg, val, ret); |
|
|
|
return ret; |
|
} |
|
|
|
static int n3000_nios_reg_read(void *context, unsigned int reg, unsigned int *val) |
|
{ |
|
struct n3000_nios *nn = context; |
|
u64 v; |
|
int ret; |
|
|
|
v = FIELD_PREP(N3000_NS_CTRL_CMD_MSK, N3000_NS_CTRL_CMD_RD) | |
|
FIELD_PREP(N3000_NS_CTRL_ADDR, reg); |
|
writeq(v, nn->base + N3000_NS_CTRL); |
|
|
|
ret = n3000_nios_poll_stat_timeout(nn->base, &v); |
|
if (ret) |
|
dev_err(nn->dev, "fail to read reg 0x%x: %d\n", reg, ret); |
|
else |
|
*val = FIELD_GET(N3000_NS_STAT_RD_DATA, v); |
|
|
|
return ret; |
|
} |
|
|
|
static const struct regmap_config n3000_nios_regbus_cfg = { |
|
.reg_bits = 32, |
|
.reg_stride = 4, |
|
.val_bits = 32, |
|
.fast_io = true, |
|
|
|
.reg_write = n3000_nios_reg_write, |
|
.reg_read = n3000_nios_reg_read, |
|
}; |
|
|
|
static int n3000_nios_probe(struct dfl_device *ddev) |
|
{ |
|
struct device *dev = &ddev->dev; |
|
struct n3000_nios *nn; |
|
int ret; |
|
|
|
nn = devm_kzalloc(dev, sizeof(*nn), GFP_KERNEL); |
|
if (!nn) |
|
return -ENOMEM; |
|
|
|
dev_set_drvdata(&ddev->dev, nn); |
|
|
|
nn->dev = dev; |
|
|
|
nn->base = devm_ioremap_resource(&ddev->dev, &ddev->mmio_res); |
|
if (IS_ERR(nn->base)) |
|
return PTR_ERR(nn->base); |
|
|
|
nn->regmap = devm_regmap_init(dev, NULL, nn, &n3000_nios_regbus_cfg); |
|
if (IS_ERR(nn->regmap)) |
|
return PTR_ERR(nn->regmap); |
|
|
|
ret = n3000_nios_init_done_check(nn); |
|
if (ret) |
|
return ret; |
|
|
|
ret = create_altera_spi_controller(nn); |
|
if (ret) |
|
dev_err(dev, "altera spi controller create failed: %d\n", ret); |
|
|
|
return ret; |
|
} |
|
|
|
static void n3000_nios_remove(struct dfl_device *ddev) |
|
{ |
|
struct n3000_nios *nn = dev_get_drvdata(&ddev->dev); |
|
|
|
destroy_altera_spi_controller(nn); |
|
} |
|
|
|
#define FME_FEATURE_ID_N3000_NIOS 0xd |
|
|
|
static const struct dfl_device_id n3000_nios_ids[] = { |
|
{ FME_ID, FME_FEATURE_ID_N3000_NIOS }, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(dfl, n3000_nios_ids); |
|
|
|
static struct dfl_driver n3000_nios_driver = { |
|
.drv = { |
|
.name = "dfl-n3000-nios", |
|
.dev_groups = n3000_nios_groups, |
|
}, |
|
.id_table = n3000_nios_ids, |
|
.probe = n3000_nios_probe, |
|
.remove = n3000_nios_remove, |
|
}; |
|
|
|
module_dfl_driver(n3000_nios_driver); |
|
|
|
MODULE_DESCRIPTION("Driver for Nios private feature on Intel PAC N3000"); |
|
MODULE_AUTHOR("Intel Corporation"); |
|
MODULE_LICENSE("GPL v2");
|
|
|