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214 lines
4.9 KiB
214 lines
4.9 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Driver for Altera Partial Reconfiguration IP Core |
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* |
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* Copyright (C) 2016-2017 Intel Corporation |
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* |
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* Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation |
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* by Alan Tull <[email protected]> |
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*/ |
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#include <linux/delay.h> |
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#include <linux/fpga/altera-pr-ip-core.h> |
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#include <linux/fpga/fpga-mgr.h> |
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#include <linux/module.h> |
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#define ALT_PR_DATA_OFST 0x00 |
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#define ALT_PR_CSR_OFST 0x04 |
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#define ALT_PR_CSR_PR_START BIT(0) |
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#define ALT_PR_CSR_STATUS_SFT 2 |
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#define ALT_PR_CSR_STATUS_MSK (7 << ALT_PR_CSR_STATUS_SFT) |
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#define ALT_PR_CSR_STATUS_NRESET (0 << ALT_PR_CSR_STATUS_SFT) |
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#define ALT_PR_CSR_STATUS_PR_ERR (1 << ALT_PR_CSR_STATUS_SFT) |
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#define ALT_PR_CSR_STATUS_CRC_ERR (2 << ALT_PR_CSR_STATUS_SFT) |
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#define ALT_PR_CSR_STATUS_BAD_BITS (3 << ALT_PR_CSR_STATUS_SFT) |
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#define ALT_PR_CSR_STATUS_PR_IN_PROG (4 << ALT_PR_CSR_STATUS_SFT) |
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#define ALT_PR_CSR_STATUS_PR_SUCCESS (5 << ALT_PR_CSR_STATUS_SFT) |
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struct alt_pr_priv { |
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void __iomem *reg_base; |
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}; |
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static enum fpga_mgr_states alt_pr_fpga_state(struct fpga_manager *mgr) |
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{ |
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struct alt_pr_priv *priv = mgr->priv; |
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const char *err = "unknown"; |
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enum fpga_mgr_states ret = FPGA_MGR_STATE_UNKNOWN; |
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u32 val; |
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val = readl(priv->reg_base + ALT_PR_CSR_OFST); |
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val &= ALT_PR_CSR_STATUS_MSK; |
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switch (val) { |
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case ALT_PR_CSR_STATUS_NRESET: |
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return FPGA_MGR_STATE_RESET; |
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case ALT_PR_CSR_STATUS_PR_ERR: |
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err = "pr error"; |
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ret = FPGA_MGR_STATE_WRITE_ERR; |
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break; |
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case ALT_PR_CSR_STATUS_CRC_ERR: |
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err = "crc error"; |
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ret = FPGA_MGR_STATE_WRITE_ERR; |
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break; |
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case ALT_PR_CSR_STATUS_BAD_BITS: |
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err = "bad bits"; |
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ret = FPGA_MGR_STATE_WRITE_ERR; |
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break; |
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case ALT_PR_CSR_STATUS_PR_IN_PROG: |
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return FPGA_MGR_STATE_WRITE; |
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case ALT_PR_CSR_STATUS_PR_SUCCESS: |
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return FPGA_MGR_STATE_OPERATING; |
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default: |
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break; |
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} |
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dev_err(&mgr->dev, "encountered error code %d (%s) in %s()\n", |
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val, err, __func__); |
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return ret; |
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} |
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static int alt_pr_fpga_write_init(struct fpga_manager *mgr, |
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struct fpga_image_info *info, |
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const char *buf, size_t count) |
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{ |
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struct alt_pr_priv *priv = mgr->priv; |
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u32 val; |
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if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { |
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dev_err(&mgr->dev, "%s Partial Reconfiguration flag not set\n", |
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__func__); |
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return -EINVAL; |
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} |
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val = readl(priv->reg_base + ALT_PR_CSR_OFST); |
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if (val & ALT_PR_CSR_PR_START) { |
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dev_err(&mgr->dev, |
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"%s Partial Reconfiguration already started\n", |
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__func__); |
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return -EINVAL; |
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} |
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writel(val | ALT_PR_CSR_PR_START, priv->reg_base + ALT_PR_CSR_OFST); |
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return 0; |
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} |
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static int alt_pr_fpga_write(struct fpga_manager *mgr, const char *buf, |
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size_t count) |
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{ |
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struct alt_pr_priv *priv = mgr->priv; |
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u32 *buffer_32 = (u32 *)buf; |
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size_t i = 0; |
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if (count <= 0) |
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return -EINVAL; |
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/* Write out the complete 32-bit chunks */ |
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while (count >= sizeof(u32)) { |
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writel(buffer_32[i++], priv->reg_base); |
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count -= sizeof(u32); |
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} |
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/* Write out remaining non 32-bit chunks */ |
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switch (count) { |
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case 3: |
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writel(buffer_32[i++] & 0x00ffffff, priv->reg_base); |
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break; |
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case 2: |
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writel(buffer_32[i++] & 0x0000ffff, priv->reg_base); |
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break; |
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case 1: |
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writel(buffer_32[i++] & 0x000000ff, priv->reg_base); |
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break; |
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case 0: |
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break; |
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default: |
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/* This will never happen */ |
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return -EFAULT; |
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} |
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if (alt_pr_fpga_state(mgr) == FPGA_MGR_STATE_WRITE_ERR) |
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return -EIO; |
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return 0; |
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} |
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static int alt_pr_fpga_write_complete(struct fpga_manager *mgr, |
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struct fpga_image_info *info) |
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{ |
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u32 i = 0; |
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do { |
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switch (alt_pr_fpga_state(mgr)) { |
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case FPGA_MGR_STATE_WRITE_ERR: |
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return -EIO; |
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case FPGA_MGR_STATE_OPERATING: |
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dev_info(&mgr->dev, |
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"successful partial reconfiguration\n"); |
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return 0; |
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default: |
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break; |
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} |
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udelay(1); |
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} while (info->config_complete_timeout_us > i++); |
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dev_err(&mgr->dev, "timed out waiting for write to complete\n"); |
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return -ETIMEDOUT; |
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} |
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static const struct fpga_manager_ops alt_pr_ops = { |
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.state = alt_pr_fpga_state, |
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.write_init = alt_pr_fpga_write_init, |
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.write = alt_pr_fpga_write, |
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.write_complete = alt_pr_fpga_write_complete, |
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}; |
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int alt_pr_register(struct device *dev, void __iomem *reg_base) |
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{ |
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struct alt_pr_priv *priv; |
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struct fpga_manager *mgr; |
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u32 val; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->reg_base = reg_base; |
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val = readl(priv->reg_base + ALT_PR_CSR_OFST); |
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dev_dbg(dev, "%s status=%d start=%d\n", __func__, |
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(val & ALT_PR_CSR_STATUS_MSK) >> ALT_PR_CSR_STATUS_SFT, |
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(int)(val & ALT_PR_CSR_PR_START)); |
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mgr = devm_fpga_mgr_create(dev, dev_name(dev), &alt_pr_ops, priv); |
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if (!mgr) |
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return -ENOMEM; |
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return devm_fpga_mgr_register(dev, mgr); |
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} |
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EXPORT_SYMBOL_GPL(alt_pr_register); |
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void alt_pr_unregister(struct device *dev) |
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{ |
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struct fpga_manager *mgr = dev_get_drvdata(dev); |
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dev_dbg(dev, "%s\n", __func__); |
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fpga_mgr_unregister(mgr); |
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} |
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EXPORT_SYMBOL_GPL(alt_pr_unregister); |
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MODULE_AUTHOR("Matthew Gerlach <[email protected]>"); |
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MODULE_DESCRIPTION("Altera Partial Reconfiguration IP Core"); |
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MODULE_LICENSE("GPL v2");
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