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303 lines
8.0 KiB
303 lines
8.0 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2006-2007 PA Semi, Inc |
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* |
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* Author: Egor Martovetsky <[email protected]> |
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* Maintained by: Olof Johansson <[email protected]> |
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* |
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* Driver for the PWRficient onchip memory controllers |
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*/ |
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#include <linux/module.h> |
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#include <linux/init.h> |
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#include <linux/pci.h> |
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#include <linux/pci_ids.h> |
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#include <linux/edac.h> |
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#include "edac_module.h" |
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#define MODULE_NAME "pasemi_edac" |
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#define MCCFG_MCEN 0x300 |
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#define MCCFG_MCEN_MMC_EN 0x00000001 |
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#define MCCFG_ERRCOR 0x388 |
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#define MCCFG_ERRCOR_RNK_FAIL_DET_EN 0x00000100 |
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#define MCCFG_ERRCOR_ECC_GEN_EN 0x00000010 |
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#define MCCFG_ERRCOR_ECC_CRR_EN 0x00000001 |
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#define MCCFG_SCRUB 0x384 |
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#define MCCFG_SCRUB_RGLR_SCRB_EN 0x00000001 |
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#define MCDEBUG_ERRCTL1 0x728 |
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#define MCDEBUG_ERRCTL1_RFL_LOG_EN 0x00080000 |
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#define MCDEBUG_ERRCTL1_MBE_LOG_EN 0x00040000 |
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#define MCDEBUG_ERRCTL1_SBE_LOG_EN 0x00020000 |
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#define MCDEBUG_ERRSTA 0x730 |
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#define MCDEBUG_ERRSTA_RFL_STATUS 0x00000004 |
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#define MCDEBUG_ERRSTA_MBE_STATUS 0x00000002 |
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#define MCDEBUG_ERRSTA_SBE_STATUS 0x00000001 |
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#define MCDEBUG_ERRCNT1 0x734 |
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#define MCDEBUG_ERRCNT1_SBE_CNT_OVRFLO 0x00000080 |
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#define MCDEBUG_ERRLOG1A 0x738 |
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#define MCDEBUG_ERRLOG1A_MERR_TYPE_M 0x30000000 |
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#define MCDEBUG_ERRLOG1A_MERR_TYPE_NONE 0x00000000 |
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#define MCDEBUG_ERRLOG1A_MERR_TYPE_SBE 0x10000000 |
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#define MCDEBUG_ERRLOG1A_MERR_TYPE_MBE 0x20000000 |
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#define MCDEBUG_ERRLOG1A_MERR_TYPE_RFL 0x30000000 |
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#define MCDEBUG_ERRLOG1A_MERR_BA_M 0x00700000 |
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#define MCDEBUG_ERRLOG1A_MERR_BA_S 20 |
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#define MCDEBUG_ERRLOG1A_MERR_CS_M 0x00070000 |
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#define MCDEBUG_ERRLOG1A_MERR_CS_S 16 |
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#define MCDEBUG_ERRLOG1A_SYNDROME_M 0x0000ffff |
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#define MCDRAM_RANKCFG 0x114 |
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#define MCDRAM_RANKCFG_EN 0x00000001 |
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#define MCDRAM_RANKCFG_TYPE_SIZE_M 0x000001c0 |
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#define MCDRAM_RANKCFG_TYPE_SIZE_S 6 |
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#define PASEMI_EDAC_NR_CSROWS 8 |
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#define PASEMI_EDAC_NR_CHANS 1 |
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#define PASEMI_EDAC_ERROR_GRAIN 64 |
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static int last_page_in_mmc; |
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static int system_mmc_id; |
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static u32 pasemi_edac_get_error_info(struct mem_ctl_info *mci) |
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{ |
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struct pci_dev *pdev = to_pci_dev(mci->pdev); |
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u32 tmp; |
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pci_read_config_dword(pdev, MCDEBUG_ERRSTA, |
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&tmp); |
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tmp &= (MCDEBUG_ERRSTA_RFL_STATUS | MCDEBUG_ERRSTA_MBE_STATUS |
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| MCDEBUG_ERRSTA_SBE_STATUS); |
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if (tmp) { |
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if (tmp & MCDEBUG_ERRSTA_SBE_STATUS) |
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pci_write_config_dword(pdev, MCDEBUG_ERRCNT1, |
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MCDEBUG_ERRCNT1_SBE_CNT_OVRFLO); |
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pci_write_config_dword(pdev, MCDEBUG_ERRSTA, tmp); |
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} |
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return tmp; |
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} |
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static void pasemi_edac_process_error_info(struct mem_ctl_info *mci, u32 errsta) |
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{ |
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struct pci_dev *pdev = to_pci_dev(mci->pdev); |
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u32 errlog1a; |
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u32 cs; |
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if (!errsta) |
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return; |
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pci_read_config_dword(pdev, MCDEBUG_ERRLOG1A, &errlog1a); |
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cs = (errlog1a & MCDEBUG_ERRLOG1A_MERR_CS_M) >> |
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MCDEBUG_ERRLOG1A_MERR_CS_S; |
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/* uncorrectable/multi-bit errors */ |
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if (errsta & (MCDEBUG_ERRSTA_MBE_STATUS | |
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MCDEBUG_ERRSTA_RFL_STATUS)) { |
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, |
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mci->csrows[cs]->first_page, 0, 0, |
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cs, 0, -1, mci->ctl_name, ""); |
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} |
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/* correctable/single-bit errors */ |
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if (errsta & MCDEBUG_ERRSTA_SBE_STATUS) |
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, |
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mci->csrows[cs]->first_page, 0, 0, |
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cs, 0, -1, mci->ctl_name, ""); |
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} |
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static void pasemi_edac_check(struct mem_ctl_info *mci) |
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{ |
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u32 errsta; |
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errsta = pasemi_edac_get_error_info(mci); |
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if (errsta) |
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pasemi_edac_process_error_info(mci, errsta); |
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} |
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static int pasemi_edac_init_csrows(struct mem_ctl_info *mci, |
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struct pci_dev *pdev, |
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enum edac_type edac_mode) |
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{ |
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struct csrow_info *csrow; |
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struct dimm_info *dimm; |
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u32 rankcfg; |
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int index; |
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for (index = 0; index < mci->nr_csrows; index++) { |
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csrow = mci->csrows[index]; |
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dimm = csrow->channels[0]->dimm; |
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pci_read_config_dword(pdev, |
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MCDRAM_RANKCFG + (index * 12), |
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&rankcfg); |
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if (!(rankcfg & MCDRAM_RANKCFG_EN)) |
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continue; |
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switch ((rankcfg & MCDRAM_RANKCFG_TYPE_SIZE_M) >> |
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MCDRAM_RANKCFG_TYPE_SIZE_S) { |
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case 0: |
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dimm->nr_pages = 128 << (20 - PAGE_SHIFT); |
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break; |
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case 1: |
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dimm->nr_pages = 256 << (20 - PAGE_SHIFT); |
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break; |
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case 2: |
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case 3: |
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dimm->nr_pages = 512 << (20 - PAGE_SHIFT); |
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break; |
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case 4: |
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dimm->nr_pages = 1024 << (20 - PAGE_SHIFT); |
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break; |
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case 5: |
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dimm->nr_pages = 2048 << (20 - PAGE_SHIFT); |
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break; |
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default: |
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edac_mc_printk(mci, KERN_ERR, |
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"Unrecognized Rank Config. rankcfg=%u\n", |
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rankcfg); |
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return -EINVAL; |
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} |
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csrow->first_page = last_page_in_mmc; |
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csrow->last_page = csrow->first_page + dimm->nr_pages - 1; |
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last_page_in_mmc += dimm->nr_pages; |
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csrow->page_mask = 0; |
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dimm->grain = PASEMI_EDAC_ERROR_GRAIN; |
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dimm->mtype = MEM_DDR; |
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dimm->dtype = DEV_UNKNOWN; |
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dimm->edac_mode = edac_mode; |
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} |
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return 0; |
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} |
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static int pasemi_edac_probe(struct pci_dev *pdev, |
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const struct pci_device_id *ent) |
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{ |
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struct mem_ctl_info *mci = NULL; |
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struct edac_mc_layer layers[2]; |
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u32 errctl1, errcor, scrub, mcen; |
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pci_read_config_dword(pdev, MCCFG_MCEN, &mcen); |
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if (!(mcen & MCCFG_MCEN_MMC_EN)) |
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return -ENODEV; |
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/* |
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* We should think about enabling other error detection later on |
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*/ |
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pci_read_config_dword(pdev, MCDEBUG_ERRCTL1, &errctl1); |
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errctl1 |= MCDEBUG_ERRCTL1_SBE_LOG_EN | |
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MCDEBUG_ERRCTL1_MBE_LOG_EN | |
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MCDEBUG_ERRCTL1_RFL_LOG_EN; |
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pci_write_config_dword(pdev, MCDEBUG_ERRCTL1, errctl1); |
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layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
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layers[0].size = PASEMI_EDAC_NR_CSROWS; |
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layers[0].is_virt_csrow = true; |
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layers[1].type = EDAC_MC_LAYER_CHANNEL; |
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layers[1].size = PASEMI_EDAC_NR_CHANS; |
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layers[1].is_virt_csrow = false; |
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mci = edac_mc_alloc(system_mmc_id++, ARRAY_SIZE(layers), layers, |
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0); |
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if (mci == NULL) |
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return -ENOMEM; |
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pci_read_config_dword(pdev, MCCFG_ERRCOR, &errcor); |
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errcor |= MCCFG_ERRCOR_RNK_FAIL_DET_EN | |
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MCCFG_ERRCOR_ECC_GEN_EN | |
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MCCFG_ERRCOR_ECC_CRR_EN; |
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mci->pdev = &pdev->dev; |
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mci->mtype_cap = MEM_FLAG_DDR | MEM_FLAG_RDDR; |
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mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; |
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mci->edac_cap = (errcor & MCCFG_ERRCOR_ECC_GEN_EN) ? |
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((errcor & MCCFG_ERRCOR_ECC_CRR_EN) ? |
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(EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_EC) : |
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EDAC_FLAG_NONE; |
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mci->mod_name = MODULE_NAME; |
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mci->dev_name = pci_name(pdev); |
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mci->ctl_name = "pasemi,pwrficient-mc"; |
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mci->edac_check = pasemi_edac_check; |
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mci->ctl_page_to_phys = NULL; |
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pci_read_config_dword(pdev, MCCFG_SCRUB, &scrub); |
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mci->scrub_cap = SCRUB_FLAG_HW_PROG | SCRUB_FLAG_HW_SRC; |
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mci->scrub_mode = |
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((errcor & MCCFG_ERRCOR_ECC_CRR_EN) ? SCRUB_FLAG_HW_SRC : 0) | |
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((scrub & MCCFG_SCRUB_RGLR_SCRB_EN) ? SCRUB_FLAG_HW_PROG : 0); |
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if (pasemi_edac_init_csrows(mci, pdev, |
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(mci->edac_cap & EDAC_FLAG_SECDED) ? |
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EDAC_SECDED : |
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((mci->edac_cap & EDAC_FLAG_EC) ? |
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EDAC_EC : EDAC_NONE))) |
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goto fail; |
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/* |
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* Clear status |
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*/ |
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pasemi_edac_get_error_info(mci); |
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if (edac_mc_add_mc(mci)) |
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goto fail; |
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/* get this far and it's successful */ |
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return 0; |
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fail: |
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edac_mc_free(mci); |
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return -ENODEV; |
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} |
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static void pasemi_edac_remove(struct pci_dev *pdev) |
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{ |
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struct mem_ctl_info *mci = edac_mc_del_mc(&pdev->dev); |
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if (!mci) |
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return; |
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edac_mc_free(mci); |
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} |
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static const struct pci_device_id pasemi_edac_pci_tbl[] = { |
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{ PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa00a) }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(pci, pasemi_edac_pci_tbl); |
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static struct pci_driver pasemi_edac_driver = { |
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.name = MODULE_NAME, |
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.probe = pasemi_edac_probe, |
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.remove = pasemi_edac_remove, |
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.id_table = pasemi_edac_pci_tbl, |
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}; |
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static int __init pasemi_edac_init(void) |
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{ |
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/* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
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opstate_init(); |
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return pci_register_driver(&pasemi_edac_driver); |
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} |
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static void __exit pasemi_edac_exit(void) |
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{ |
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pci_unregister_driver(&pasemi_edac_driver); |
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} |
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module_init(pasemi_edac_init); |
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module_exit(pasemi_edac_exit); |
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MODULE_LICENSE("GPL"); |
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MODULE_AUTHOR("Egor Martovetsky <[email protected]>"); |
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MODULE_DESCRIPTION("MC support for PA Semi PWRficient memory controller"); |
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module_param(edac_op_state, int, 0444); |
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MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |
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