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603 lines
16 KiB
603 lines
16 KiB
/* |
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* Intel e7xxx Memory Controller kernel module |
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* (C) 2003 Linux Networx (http://lnxi.com) |
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* This file may be distributed under the terms of the |
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* GNU General Public License. |
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* |
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* See "enum e7xxx_chips" below for supported chipsets |
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* |
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* Written by Thayne Harbaugh |
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* Based on work by Dan Hollis <goemon at anime dot net> and others. |
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* http://www.anime.net/~goemon/linux-ecc/ |
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* |
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* Datasheet: |
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* http://www.intel.com/content/www/us/en/chipsets/e7501-chipset-memory-controller-hub-datasheet.html |
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* |
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* Contributors: |
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* Eric Biederman (Linux Networx) |
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* Tom Zimmerman (Linux Networx) |
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* Jim Garlick (Lawrence Livermore National Labs) |
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* Dave Peterson (Lawrence Livermore National Labs) |
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* That One Guy (Some other place) |
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* Wang Zhenyu (intel.com) |
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* |
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* $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $ |
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* |
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*/ |
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#include <linux/module.h> |
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#include <linux/init.h> |
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#include <linux/pci.h> |
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#include <linux/pci_ids.h> |
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#include <linux/edac.h> |
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#include "edac_module.h" |
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#define EDAC_MOD_STR "e7xxx_edac" |
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#define e7xxx_printk(level, fmt, arg...) \ |
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edac_printk(level, "e7xxx", fmt, ##arg) |
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#define e7xxx_mc_printk(mci, level, fmt, arg...) \ |
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edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg) |
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#ifndef PCI_DEVICE_ID_INTEL_7205_0 |
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#define PCI_DEVICE_ID_INTEL_7205_0 0x255d |
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#endif /* PCI_DEVICE_ID_INTEL_7205_0 */ |
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#ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR |
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#define PCI_DEVICE_ID_INTEL_7205_1_ERR 0x2551 |
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#endif /* PCI_DEVICE_ID_INTEL_7205_1_ERR */ |
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#ifndef PCI_DEVICE_ID_INTEL_7500_0 |
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#define PCI_DEVICE_ID_INTEL_7500_0 0x2540 |
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#endif /* PCI_DEVICE_ID_INTEL_7500_0 */ |
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#ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR |
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#define PCI_DEVICE_ID_INTEL_7500_1_ERR 0x2541 |
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#endif /* PCI_DEVICE_ID_INTEL_7500_1_ERR */ |
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#ifndef PCI_DEVICE_ID_INTEL_7501_0 |
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#define PCI_DEVICE_ID_INTEL_7501_0 0x254c |
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#endif /* PCI_DEVICE_ID_INTEL_7501_0 */ |
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#ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR |
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#define PCI_DEVICE_ID_INTEL_7501_1_ERR 0x2541 |
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#endif /* PCI_DEVICE_ID_INTEL_7501_1_ERR */ |
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#ifndef PCI_DEVICE_ID_INTEL_7505_0 |
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#define PCI_DEVICE_ID_INTEL_7505_0 0x2550 |
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#endif /* PCI_DEVICE_ID_INTEL_7505_0 */ |
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#ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR |
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#define PCI_DEVICE_ID_INTEL_7505_1_ERR 0x2551 |
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#endif /* PCI_DEVICE_ID_INTEL_7505_1_ERR */ |
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#define E7XXX_NR_CSROWS 8 /* number of csrows */ |
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#define E7XXX_NR_DIMMS 8 /* 2 channels, 4 dimms/channel */ |
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|
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/* E7XXX register addresses - device 0 function 0 */ |
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#define E7XXX_DRB 0x60 /* DRAM row boundary register (8b) */ |
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#define E7XXX_DRA 0x70 /* DRAM row attribute register (8b) */ |
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/* |
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* 31 Device width row 7 0=x8 1=x4 |
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* 27 Device width row 6 |
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* 23 Device width row 5 |
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* 19 Device width row 4 |
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* 15 Device width row 3 |
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* 11 Device width row 2 |
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* 7 Device width row 1 |
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* 3 Device width row 0 |
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*/ |
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#define E7XXX_DRC 0x7C /* DRAM controller mode reg (32b) */ |
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/* |
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* 22 Number channels 0=1,1=2 |
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* 19:18 DRB Granularity 32/64MB |
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*/ |
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#define E7XXX_TOLM 0xC4 /* DRAM top of low memory reg (16b) */ |
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#define E7XXX_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */ |
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#define E7XXX_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */ |
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/* E7XXX register addresses - device 0 function 1 */ |
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#define E7XXX_DRAM_FERR 0x80 /* DRAM first error register (8b) */ |
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#define E7XXX_DRAM_NERR 0x82 /* DRAM next error register (8b) */ |
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#define E7XXX_DRAM_CELOG_ADD 0xA0 /* DRAM first correctable memory */ |
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/* error address register (32b) */ |
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/* |
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* 31:28 Reserved |
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* 27:6 CE address (4k block 33:12) |
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* 5:0 Reserved |
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*/ |
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#define E7XXX_DRAM_UELOG_ADD 0xB0 /* DRAM first uncorrectable memory */ |
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/* error address register (32b) */ |
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/* |
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* 31:28 Reserved |
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* 27:6 CE address (4k block 33:12) |
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* 5:0 Reserved |
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*/ |
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#define E7XXX_DRAM_CELOG_SYNDROME 0xD0 /* DRAM first correctable memory */ |
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/* error syndrome register (16b) */ |
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enum e7xxx_chips { |
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E7500 = 0, |
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E7501, |
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E7505, |
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E7205, |
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}; |
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struct e7xxx_pvt { |
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struct pci_dev *bridge_ck; |
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u32 tolm; |
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u32 remapbase; |
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u32 remaplimit; |
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const struct e7xxx_dev_info *dev_info; |
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}; |
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struct e7xxx_dev_info { |
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u16 err_dev; |
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const char *ctl_name; |
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}; |
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struct e7xxx_error_info { |
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u8 dram_ferr; |
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u8 dram_nerr; |
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u32 dram_celog_add; |
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u16 dram_celog_syndrome; |
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u32 dram_uelog_add; |
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}; |
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static struct edac_pci_ctl_info *e7xxx_pci; |
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static const struct e7xxx_dev_info e7xxx_devs[] = { |
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[E7500] = { |
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.err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR, |
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.ctl_name = "E7500"}, |
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[E7501] = { |
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.err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR, |
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.ctl_name = "E7501"}, |
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[E7505] = { |
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.err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR, |
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.ctl_name = "E7505"}, |
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[E7205] = { |
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.err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR, |
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.ctl_name = "E7205"}, |
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}; |
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/* FIXME - is this valid for both SECDED and S4ECD4ED? */ |
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static inline int e7xxx_find_channel(u16 syndrome) |
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{ |
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edac_dbg(3, "\n"); |
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if ((syndrome & 0xff00) == 0) |
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return 0; |
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if ((syndrome & 0x00ff) == 0) |
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return 1; |
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if ((syndrome & 0xf000) == 0 || (syndrome & 0x0f00) == 0) |
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return 0; |
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return 1; |
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} |
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static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci, |
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unsigned long page) |
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{ |
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u32 remap; |
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struct e7xxx_pvt *pvt = (struct e7xxx_pvt *)mci->pvt_info; |
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edac_dbg(3, "\n"); |
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if ((page < pvt->tolm) || |
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((page >= 0x100000) && (page < pvt->remapbase))) |
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return page; |
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remap = (page - pvt->tolm) + pvt->remapbase; |
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if (remap < pvt->remaplimit) |
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return remap; |
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e7xxx_printk(KERN_ERR, "Invalid page %lx - out of range\n", page); |
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return pvt->tolm - 1; |
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} |
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static void process_ce(struct mem_ctl_info *mci, struct e7xxx_error_info *info) |
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{ |
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u32 error_1b, page; |
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u16 syndrome; |
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int row; |
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int channel; |
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edac_dbg(3, "\n"); |
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/* read the error address */ |
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error_1b = info->dram_celog_add; |
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/* FIXME - should use PAGE_SHIFT */ |
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page = error_1b >> 6; /* convert the address to 4k page */ |
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/* read the syndrome */ |
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syndrome = info->dram_celog_syndrome; |
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/* FIXME - check for -1 */ |
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row = edac_mc_find_csrow_by_page(mci, page); |
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/* convert syndrome to channel */ |
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channel = e7xxx_find_channel(syndrome); |
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, page, 0, syndrome, |
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row, channel, -1, "e7xxx CE", ""); |
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} |
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static void process_ce_no_info(struct mem_ctl_info *mci) |
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{ |
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edac_dbg(3, "\n"); |
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0, -1, -1, -1, |
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"e7xxx CE log register overflow", ""); |
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} |
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static void process_ue(struct mem_ctl_info *mci, struct e7xxx_error_info *info) |
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{ |
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u32 error_2b, block_page; |
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int row; |
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edac_dbg(3, "\n"); |
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/* read the error address */ |
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error_2b = info->dram_uelog_add; |
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/* FIXME - should use PAGE_SHIFT */ |
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block_page = error_2b >> 6; /* convert to 4k address */ |
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row = edac_mc_find_csrow_by_page(mci, block_page); |
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, block_page, 0, 0, |
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row, -1, -1, "e7xxx UE", ""); |
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} |
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static void process_ue_no_info(struct mem_ctl_info *mci) |
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{ |
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edac_dbg(3, "\n"); |
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, -1, -1, -1, |
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"e7xxx UE log register overflow", ""); |
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} |
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static void e7xxx_get_error_info(struct mem_ctl_info *mci, |
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struct e7xxx_error_info *info) |
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{ |
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struct e7xxx_pvt *pvt; |
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pvt = (struct e7xxx_pvt *)mci->pvt_info; |
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pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR, &info->dram_ferr); |
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pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR, &info->dram_nerr); |
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if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) { |
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pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD, |
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&info->dram_celog_add); |
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pci_read_config_word(pvt->bridge_ck, |
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E7XXX_DRAM_CELOG_SYNDROME, |
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&info->dram_celog_syndrome); |
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} |
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if ((info->dram_ferr & 2) || (info->dram_nerr & 2)) |
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pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD, |
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&info->dram_uelog_add); |
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if (info->dram_ferr & 3) |
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pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03); |
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if (info->dram_nerr & 3) |
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pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03); |
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} |
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static int e7xxx_process_error_info(struct mem_ctl_info *mci, |
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struct e7xxx_error_info *info, |
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int handle_errors) |
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{ |
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int error_found; |
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error_found = 0; |
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/* decode and report errors */ |
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if (info->dram_ferr & 1) { /* check first error correctable */ |
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error_found = 1; |
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if (handle_errors) |
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process_ce(mci, info); |
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} |
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if (info->dram_ferr & 2) { /* check first error uncorrectable */ |
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error_found = 1; |
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if (handle_errors) |
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process_ue(mci, info); |
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} |
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if (info->dram_nerr & 1) { /* check next error correctable */ |
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error_found = 1; |
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if (handle_errors) { |
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if (info->dram_ferr & 1) |
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process_ce_no_info(mci); |
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else |
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process_ce(mci, info); |
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} |
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} |
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if (info->dram_nerr & 2) { /* check next error uncorrectable */ |
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error_found = 1; |
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if (handle_errors) { |
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if (info->dram_ferr & 2) |
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process_ue_no_info(mci); |
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else |
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process_ue(mci, info); |
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} |
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} |
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return error_found; |
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} |
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static void e7xxx_check(struct mem_ctl_info *mci) |
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{ |
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struct e7xxx_error_info info; |
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e7xxx_get_error_info(mci, &info); |
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e7xxx_process_error_info(mci, &info, 1); |
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} |
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/* Return 1 if dual channel mode is active. Else return 0. */ |
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static inline int dual_channel_active(u32 drc, int dev_idx) |
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{ |
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return (dev_idx == E7501) ? ((drc >> 22) & 0x1) : 1; |
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} |
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/* Return DRB granularity (0=32mb, 1=64mb). */ |
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static inline int drb_granularity(u32 drc, int dev_idx) |
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{ |
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/* only e7501 can be single channel */ |
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return (dev_idx == E7501) ? ((drc >> 18) & 0x3) : 1; |
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} |
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static void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, |
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int dev_idx, u32 drc) |
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{ |
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unsigned long last_cumul_size; |
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int index, j; |
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u8 value; |
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u32 dra, cumul_size, nr_pages; |
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int drc_chan, drc_drbg, drc_ddim, mem_dev; |
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struct csrow_info *csrow; |
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struct dimm_info *dimm; |
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enum edac_type edac_mode; |
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pci_read_config_dword(pdev, E7XXX_DRA, &dra); |
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drc_chan = dual_channel_active(drc, dev_idx); |
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drc_drbg = drb_granularity(drc, dev_idx); |
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drc_ddim = (drc >> 20) & 0x3; |
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last_cumul_size = 0; |
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|
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/* The dram row boundary (DRB) reg values are boundary address |
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* for each DRAM row with a granularity of 32 or 64MB (single/dual |
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* channel operation). DRB regs are cumulative; therefore DRB7 will |
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* contain the total memory contained in all eight rows. |
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*/ |
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for (index = 0; index < mci->nr_csrows; index++) { |
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/* mem_dev 0=x8, 1=x4 */ |
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mem_dev = (dra >> (index * 4 + 3)) & 0x1; |
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csrow = mci->csrows[index]; |
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pci_read_config_byte(pdev, E7XXX_DRB + index, &value); |
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/* convert a 64 or 32 MiB DRB to a page size. */ |
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cumul_size = value << (25 + drc_drbg - PAGE_SHIFT); |
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edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size); |
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if (cumul_size == last_cumul_size) |
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continue; /* not populated */ |
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csrow->first_page = last_cumul_size; |
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csrow->last_page = cumul_size - 1; |
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nr_pages = cumul_size - last_cumul_size; |
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last_cumul_size = cumul_size; |
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/* |
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* if single channel or x8 devices then SECDED |
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* if dual channel and x4 then S4ECD4ED |
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*/ |
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if (drc_ddim) { |
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if (drc_chan && mem_dev) { |
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edac_mode = EDAC_S4ECD4ED; |
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mci->edac_cap |= EDAC_FLAG_S4ECD4ED; |
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} else { |
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edac_mode = EDAC_SECDED; |
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mci->edac_cap |= EDAC_FLAG_SECDED; |
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} |
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} else |
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edac_mode = EDAC_NONE; |
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for (j = 0; j < drc_chan + 1; j++) { |
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dimm = csrow->channels[j]->dimm; |
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dimm->nr_pages = nr_pages / (drc_chan + 1); |
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dimm->grain = 1 << 12; /* 4KiB - resolution of CELOG */ |
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dimm->mtype = MEM_RDDR; /* only one type supported */ |
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dimm->dtype = mem_dev ? DEV_X4 : DEV_X8; |
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dimm->edac_mode = edac_mode; |
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} |
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} |
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} |
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static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx) |
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{ |
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u16 pci_data; |
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struct mem_ctl_info *mci = NULL; |
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struct edac_mc_layer layers[2]; |
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struct e7xxx_pvt *pvt = NULL; |
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u32 drc; |
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int drc_chan; |
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struct e7xxx_error_info discard; |
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edac_dbg(0, "mci\n"); |
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pci_read_config_dword(pdev, E7XXX_DRC, &drc); |
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drc_chan = dual_channel_active(drc, dev_idx); |
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/* |
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* According with the datasheet, this device has a maximum of |
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* 4 DIMMS per channel, either single-rank or dual-rank. So, the |
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* total amount of dimms is 8 (E7XXX_NR_DIMMS). |
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* That means that the DIMM is mapped as CSROWs, and the channel |
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* will map the rank. So, an error to either channel should be |
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* attributed to the same dimm. |
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*/ |
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layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
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layers[0].size = E7XXX_NR_CSROWS; |
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layers[0].is_virt_csrow = true; |
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layers[1].type = EDAC_MC_LAYER_CHANNEL; |
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layers[1].size = drc_chan + 1; |
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layers[1].is_virt_csrow = false; |
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mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); |
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if (mci == NULL) |
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return -ENOMEM; |
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edac_dbg(3, "init mci\n"); |
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mci->mtype_cap = MEM_FLAG_RDDR; |
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mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED | |
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EDAC_FLAG_S4ECD4ED; |
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/* FIXME - what if different memory types are in different csrows? */ |
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mci->mod_name = EDAC_MOD_STR; |
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mci->pdev = &pdev->dev; |
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edac_dbg(3, "init pvt\n"); |
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pvt = (struct e7xxx_pvt *)mci->pvt_info; |
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pvt->dev_info = &e7xxx_devs[dev_idx]; |
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pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL, |
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pvt->dev_info->err_dev, pvt->bridge_ck); |
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|
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if (!pvt->bridge_ck) { |
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e7xxx_printk(KERN_ERR, "error reporting device not found:" |
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"vendor %x device 0x%x (broken BIOS?)\n", |
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PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev); |
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goto fail0; |
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} |
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edac_dbg(3, "more mci init\n"); |
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mci->ctl_name = pvt->dev_info->ctl_name; |
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mci->dev_name = pci_name(pdev); |
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mci->edac_check = e7xxx_check; |
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mci->ctl_page_to_phys = ctl_page_to_phys; |
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e7xxx_init_csrows(mci, pdev, dev_idx, drc); |
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mci->edac_cap |= EDAC_FLAG_NONE; |
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edac_dbg(3, "tolm, remapbase, remaplimit\n"); |
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/* load the top of low memory, remap base, and remap limit vars */ |
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pci_read_config_word(pdev, E7XXX_TOLM, &pci_data); |
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pvt->tolm = ((u32) pci_data) << 4; |
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pci_read_config_word(pdev, E7XXX_REMAPBASE, &pci_data); |
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pvt->remapbase = ((u32) pci_data) << 14; |
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pci_read_config_word(pdev, E7XXX_REMAPLIMIT, &pci_data); |
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pvt->remaplimit = ((u32) pci_data) << 14; |
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e7xxx_printk(KERN_INFO, |
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"tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm, |
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pvt->remapbase, pvt->remaplimit); |
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|
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/* clear any pending errors, or initial state bits */ |
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e7xxx_get_error_info(mci, &discard); |
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|
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/* Here we assume that we will never see multiple instances of this |
|
* type of memory controller. The ID is therefore hardcoded to 0. |
|
*/ |
|
if (edac_mc_add_mc(mci)) { |
|
edac_dbg(3, "failed edac_mc_add_mc()\n"); |
|
goto fail1; |
|
} |
|
|
|
/* allocating generic PCI control info */ |
|
e7xxx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); |
|
if (!e7xxx_pci) { |
|
printk(KERN_WARNING |
|
"%s(): Unable to create PCI control\n", |
|
__func__); |
|
printk(KERN_WARNING |
|
"%s(): PCI error report via EDAC not setup\n", |
|
__func__); |
|
} |
|
|
|
/* get this far and it's successful */ |
|
edac_dbg(3, "success\n"); |
|
return 0; |
|
|
|
fail1: |
|
pci_dev_put(pvt->bridge_ck); |
|
|
|
fail0: |
|
edac_mc_free(mci); |
|
|
|
return -ENODEV; |
|
} |
|
|
|
/* returns count (>= 0), or negative on error */ |
|
static int e7xxx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
|
{ |
|
edac_dbg(0, "\n"); |
|
|
|
/* wake up and enable device */ |
|
return pci_enable_device(pdev) ? |
|
-EIO : e7xxx_probe1(pdev, ent->driver_data); |
|
} |
|
|
|
static void e7xxx_remove_one(struct pci_dev *pdev) |
|
{ |
|
struct mem_ctl_info *mci; |
|
struct e7xxx_pvt *pvt; |
|
|
|
edac_dbg(0, "\n"); |
|
|
|
if (e7xxx_pci) |
|
edac_pci_release_generic_ctl(e7xxx_pci); |
|
|
|
if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) |
|
return; |
|
|
|
pvt = (struct e7xxx_pvt *)mci->pvt_info; |
|
pci_dev_put(pvt->bridge_ck); |
|
edac_mc_free(mci); |
|
} |
|
|
|
static const struct pci_device_id e7xxx_pci_tbl[] = { |
|
{ |
|
PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
|
E7205}, |
|
{ |
|
PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
|
E7500}, |
|
{ |
|
PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
|
E7501}, |
|
{ |
|
PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
|
E7505}, |
|
{ |
|
0, |
|
} /* 0 terminated list. */ |
|
}; |
|
|
|
MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl); |
|
|
|
static struct pci_driver e7xxx_driver = { |
|
.name = EDAC_MOD_STR, |
|
.probe = e7xxx_init_one, |
|
.remove = e7xxx_remove_one, |
|
.id_table = e7xxx_pci_tbl, |
|
}; |
|
|
|
static int __init e7xxx_init(void) |
|
{ |
|
/* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
|
opstate_init(); |
|
|
|
return pci_register_driver(&e7xxx_driver); |
|
} |
|
|
|
static void __exit e7xxx_exit(void) |
|
{ |
|
pci_unregister_driver(&e7xxx_driver); |
|
} |
|
|
|
module_init(e7xxx_init); |
|
module_exit(e7xxx_exit); |
|
|
|
MODULE_LICENSE("GPL"); |
|
MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n" |
|
"Based on.work by Dan Hollis et al"); |
|
MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers"); |
|
module_param(edac_op_state, int, 0444); |
|
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
|
|
|