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656 lines
16 KiB
656 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* EDAC driver for DMC-520 memory controller. |
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* |
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* The driver supports 10 interrupt lines, |
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* though only dram_ecc_errc and dram_ecc_errd are currently handled. |
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* |
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* Authors: Rui Zhao <[email protected]> |
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* Lei Wang <[email protected]> |
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* Shiping Ji <[email protected]> |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/edac.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/spinlock.h> |
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#include "edac_mc.h" |
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/* DMC-520 registers */ |
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#define REG_OFFSET_FEATURE_CONFIG 0x130 |
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#define REG_OFFSET_ECC_ERRC_COUNT_31_00 0x158 |
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#define REG_OFFSET_ECC_ERRC_COUNT_63_32 0x15C |
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#define REG_OFFSET_ECC_ERRD_COUNT_31_00 0x160 |
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#define REG_OFFSET_ECC_ERRD_COUNT_63_32 0x164 |
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#define REG_OFFSET_INTERRUPT_CONTROL 0x500 |
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#define REG_OFFSET_INTERRUPT_CLR 0x508 |
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#define REG_OFFSET_INTERRUPT_STATUS 0x510 |
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#define REG_OFFSET_DRAM_ECC_ERRC_INT_INFO_31_00 0x528 |
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#define REG_OFFSET_DRAM_ECC_ERRC_INT_INFO_63_32 0x52C |
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#define REG_OFFSET_DRAM_ECC_ERRD_INT_INFO_31_00 0x530 |
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#define REG_OFFSET_DRAM_ECC_ERRD_INT_INFO_63_32 0x534 |
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#define REG_OFFSET_ADDRESS_CONTROL_NOW 0x1010 |
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#define REG_OFFSET_MEMORY_TYPE_NOW 0x1128 |
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#define REG_OFFSET_SCRUB_CONTROL0_NOW 0x1170 |
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#define REG_OFFSET_FORMAT_CONTROL 0x18 |
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/* DMC-520 types, masks and bitfields */ |
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#define RAM_ECC_INT_CE_BIT BIT(0) |
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#define RAM_ECC_INT_UE_BIT BIT(1) |
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#define DRAM_ECC_INT_CE_BIT BIT(2) |
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#define DRAM_ECC_INT_UE_BIT BIT(3) |
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#define FAILED_ACCESS_INT_BIT BIT(4) |
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#define FAILED_PROG_INT_BIT BIT(5) |
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#define LINK_ERR_INT_BIT BIT(6) |
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#define TEMPERATURE_EVENT_INT_BIT BIT(7) |
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#define ARCH_FSM_INT_BIT BIT(8) |
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#define PHY_REQUEST_INT_BIT BIT(9) |
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#define MEMORY_WIDTH_MASK GENMASK(1, 0) |
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#define SCRUB_TRIGGER0_NEXT_MASK GENMASK(1, 0) |
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#define REG_FIELD_DRAM_ECC_ENABLED GENMASK(1, 0) |
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#define REG_FIELD_MEMORY_TYPE GENMASK(2, 0) |
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#define REG_FIELD_DEVICE_WIDTH GENMASK(9, 8) |
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#define REG_FIELD_ADDRESS_CONTROL_COL GENMASK(2, 0) |
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#define REG_FIELD_ADDRESS_CONTROL_ROW GENMASK(10, 8) |
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#define REG_FIELD_ADDRESS_CONTROL_BANK GENMASK(18, 16) |
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#define REG_FIELD_ADDRESS_CONTROL_RANK GENMASK(25, 24) |
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#define REG_FIELD_ERR_INFO_LOW_VALID BIT(0) |
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#define REG_FIELD_ERR_INFO_LOW_COL GENMASK(10, 1) |
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#define REG_FIELD_ERR_INFO_LOW_ROW GENMASK(28, 11) |
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#define REG_FIELD_ERR_INFO_LOW_RANK GENMASK(31, 29) |
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#define REG_FIELD_ERR_INFO_HIGH_BANK GENMASK(3, 0) |
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#define REG_FIELD_ERR_INFO_HIGH_VALID BIT(31) |
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#define DRAM_ADDRESS_CONTROL_MIN_COL_BITS 8 |
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#define DRAM_ADDRESS_CONTROL_MIN_ROW_BITS 11 |
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#define DMC520_SCRUB_TRIGGER_ERR_DETECT 2 |
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#define DMC520_SCRUB_TRIGGER_IDLE 3 |
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/* Driver settings */ |
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/* |
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* The max-length message would be: "rank:7 bank:15 row:262143 col:1023". |
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* Max length is 34. Using a 40-size buffer is enough. |
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*/ |
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#define DMC520_MSG_BUF_SIZE 40 |
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#define EDAC_MOD_NAME "dmc520-edac" |
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#define EDAC_CTL_NAME "dmc520" |
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/* the data bus width for the attached memory chips. */ |
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enum dmc520_mem_width { |
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MEM_WIDTH_X32 = 2, |
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MEM_WIDTH_X64 = 3 |
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}; |
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/* memory type */ |
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enum dmc520_mem_type { |
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MEM_TYPE_DDR3 = 1, |
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MEM_TYPE_DDR4 = 2 |
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}; |
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/* memory device width */ |
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enum dmc520_dev_width { |
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DEV_WIDTH_X4 = 0, |
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DEV_WIDTH_X8 = 1, |
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DEV_WIDTH_X16 = 2 |
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}; |
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struct ecc_error_info { |
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u32 col; |
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u32 row; |
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u32 bank; |
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u32 rank; |
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}; |
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/* The interrupt config */ |
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struct dmc520_irq_config { |
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char *name; |
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int mask; |
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}; |
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/* The interrupt mappings */ |
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static struct dmc520_irq_config dmc520_irq_configs[] = { |
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{ |
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.name = "ram_ecc_errc", |
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.mask = RAM_ECC_INT_CE_BIT |
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}, |
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{ |
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.name = "ram_ecc_errd", |
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.mask = RAM_ECC_INT_UE_BIT |
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}, |
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{ |
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.name = "dram_ecc_errc", |
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.mask = DRAM_ECC_INT_CE_BIT |
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}, |
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{ |
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.name = "dram_ecc_errd", |
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.mask = DRAM_ECC_INT_UE_BIT |
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}, |
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{ |
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.name = "failed_access", |
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.mask = FAILED_ACCESS_INT_BIT |
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}, |
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{ |
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.name = "failed_prog", |
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.mask = FAILED_PROG_INT_BIT |
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}, |
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{ |
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.name = "link_err", |
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.mask = LINK_ERR_INT_BIT |
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}, |
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{ |
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.name = "temperature_event", |
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.mask = TEMPERATURE_EVENT_INT_BIT |
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}, |
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{ |
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.name = "arch_fsm", |
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.mask = ARCH_FSM_INT_BIT |
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}, |
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{ |
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.name = "phy_request", |
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.mask = PHY_REQUEST_INT_BIT |
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} |
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}; |
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#define NUMBER_OF_IRQS ARRAY_SIZE(dmc520_irq_configs) |
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/* |
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* The EDAC driver private data. |
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* error_lock is to protect concurrent writes to the mci->error_desc through |
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* edac_mc_handle_error(). |
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*/ |
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struct dmc520_edac { |
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void __iomem *reg_base; |
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spinlock_t error_lock; |
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u32 mem_width_in_bytes; |
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int irqs[NUMBER_OF_IRQS]; |
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int masks[NUMBER_OF_IRQS]; |
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}; |
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static int dmc520_mc_idx; |
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static u32 dmc520_read_reg(struct dmc520_edac *pvt, u32 offset) |
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{ |
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return readl(pvt->reg_base + offset); |
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} |
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static void dmc520_write_reg(struct dmc520_edac *pvt, u32 val, u32 offset) |
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{ |
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writel(val, pvt->reg_base + offset); |
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} |
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static u32 dmc520_calc_dram_ecc_error(u32 value) |
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{ |
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u32 total = 0; |
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/* Each rank's error counter takes one byte. */ |
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while (value > 0) { |
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total += (value & 0xFF); |
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value >>= 8; |
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} |
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return total; |
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} |
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static u32 dmc520_get_dram_ecc_error_count(struct dmc520_edac *pvt, |
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bool is_ce) |
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{ |
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u32 reg_offset_low, reg_offset_high; |
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u32 err_low, err_high; |
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u32 err_count; |
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reg_offset_low = is_ce ? REG_OFFSET_ECC_ERRC_COUNT_31_00 : |
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REG_OFFSET_ECC_ERRD_COUNT_31_00; |
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reg_offset_high = is_ce ? REG_OFFSET_ECC_ERRC_COUNT_63_32 : |
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REG_OFFSET_ECC_ERRD_COUNT_63_32; |
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err_low = dmc520_read_reg(pvt, reg_offset_low); |
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err_high = dmc520_read_reg(pvt, reg_offset_high); |
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/* Reset error counters */ |
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dmc520_write_reg(pvt, 0, reg_offset_low); |
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dmc520_write_reg(pvt, 0, reg_offset_high); |
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err_count = dmc520_calc_dram_ecc_error(err_low) + |
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dmc520_calc_dram_ecc_error(err_high); |
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return err_count; |
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} |
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static void dmc520_get_dram_ecc_error_info(struct dmc520_edac *pvt, |
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bool is_ce, |
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struct ecc_error_info *info) |
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{ |
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u32 reg_offset_low, reg_offset_high; |
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u32 reg_val_low, reg_val_high; |
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bool valid; |
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reg_offset_low = is_ce ? REG_OFFSET_DRAM_ECC_ERRC_INT_INFO_31_00 : |
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REG_OFFSET_DRAM_ECC_ERRD_INT_INFO_31_00; |
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reg_offset_high = is_ce ? REG_OFFSET_DRAM_ECC_ERRC_INT_INFO_63_32 : |
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REG_OFFSET_DRAM_ECC_ERRD_INT_INFO_63_32; |
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reg_val_low = dmc520_read_reg(pvt, reg_offset_low); |
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reg_val_high = dmc520_read_reg(pvt, reg_offset_high); |
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valid = (FIELD_GET(REG_FIELD_ERR_INFO_LOW_VALID, reg_val_low) != 0) && |
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(FIELD_GET(REG_FIELD_ERR_INFO_HIGH_VALID, reg_val_high) != 0); |
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if (valid) { |
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info->col = FIELD_GET(REG_FIELD_ERR_INFO_LOW_COL, reg_val_low); |
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info->row = FIELD_GET(REG_FIELD_ERR_INFO_LOW_ROW, reg_val_low); |
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info->rank = FIELD_GET(REG_FIELD_ERR_INFO_LOW_RANK, reg_val_low); |
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info->bank = FIELD_GET(REG_FIELD_ERR_INFO_HIGH_BANK, reg_val_high); |
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} else { |
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memset(info, 0, sizeof(*info)); |
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} |
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} |
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static bool dmc520_is_ecc_enabled(void __iomem *reg_base) |
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{ |
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u32 reg_val = readl(reg_base + REG_OFFSET_FEATURE_CONFIG); |
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return FIELD_GET(REG_FIELD_DRAM_ECC_ENABLED, reg_val); |
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} |
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static enum scrub_type dmc520_get_scrub_type(struct dmc520_edac *pvt) |
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{ |
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enum scrub_type type = SCRUB_NONE; |
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u32 reg_val, scrub_cfg; |
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reg_val = dmc520_read_reg(pvt, REG_OFFSET_SCRUB_CONTROL0_NOW); |
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scrub_cfg = FIELD_GET(SCRUB_TRIGGER0_NEXT_MASK, reg_val); |
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if (scrub_cfg == DMC520_SCRUB_TRIGGER_ERR_DETECT || |
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scrub_cfg == DMC520_SCRUB_TRIGGER_IDLE) |
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type = SCRUB_HW_PROG; |
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return type; |
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} |
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/* Get the memory data bus width, in number of bytes. */ |
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static u32 dmc520_get_memory_width(struct dmc520_edac *pvt) |
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{ |
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enum dmc520_mem_width mem_width_field; |
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u32 mem_width_in_bytes = 0; |
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u32 reg_val; |
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reg_val = dmc520_read_reg(pvt, REG_OFFSET_FORMAT_CONTROL); |
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mem_width_field = FIELD_GET(MEMORY_WIDTH_MASK, reg_val); |
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if (mem_width_field == MEM_WIDTH_X32) |
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mem_width_in_bytes = 4; |
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else if (mem_width_field == MEM_WIDTH_X64) |
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mem_width_in_bytes = 8; |
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return mem_width_in_bytes; |
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} |
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static enum mem_type dmc520_get_mtype(struct dmc520_edac *pvt) |
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{ |
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enum mem_type mt = MEM_UNKNOWN; |
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enum dmc520_mem_type type; |
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u32 reg_val; |
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reg_val = dmc520_read_reg(pvt, REG_OFFSET_MEMORY_TYPE_NOW); |
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type = FIELD_GET(REG_FIELD_MEMORY_TYPE, reg_val); |
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switch (type) { |
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case MEM_TYPE_DDR3: |
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mt = MEM_DDR3; |
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break; |
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case MEM_TYPE_DDR4: |
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mt = MEM_DDR4; |
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break; |
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} |
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return mt; |
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} |
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static enum dev_type dmc520_get_dtype(struct dmc520_edac *pvt) |
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{ |
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enum dmc520_dev_width device_width; |
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enum dev_type dt = DEV_UNKNOWN; |
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u32 reg_val; |
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reg_val = dmc520_read_reg(pvt, REG_OFFSET_MEMORY_TYPE_NOW); |
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device_width = FIELD_GET(REG_FIELD_DEVICE_WIDTH, reg_val); |
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switch (device_width) { |
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case DEV_WIDTH_X4: |
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dt = DEV_X4; |
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break; |
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case DEV_WIDTH_X8: |
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dt = DEV_X8; |
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break; |
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case DEV_WIDTH_X16: |
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dt = DEV_X16; |
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break; |
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} |
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return dt; |
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} |
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static u32 dmc520_get_rank_count(void __iomem *reg_base) |
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{ |
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u32 reg_val, rank_bits; |
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reg_val = readl(reg_base + REG_OFFSET_ADDRESS_CONTROL_NOW); |
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rank_bits = FIELD_GET(REG_FIELD_ADDRESS_CONTROL_RANK, reg_val); |
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return BIT(rank_bits); |
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} |
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static u64 dmc520_get_rank_size(struct dmc520_edac *pvt) |
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{ |
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u32 reg_val, col_bits, row_bits, bank_bits; |
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reg_val = dmc520_read_reg(pvt, REG_OFFSET_ADDRESS_CONTROL_NOW); |
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col_bits = FIELD_GET(REG_FIELD_ADDRESS_CONTROL_COL, reg_val) + |
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DRAM_ADDRESS_CONTROL_MIN_COL_BITS; |
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row_bits = FIELD_GET(REG_FIELD_ADDRESS_CONTROL_ROW, reg_val) + |
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DRAM_ADDRESS_CONTROL_MIN_ROW_BITS; |
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bank_bits = FIELD_GET(REG_FIELD_ADDRESS_CONTROL_BANK, reg_val); |
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return (u64)pvt->mem_width_in_bytes << (col_bits + row_bits + bank_bits); |
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} |
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static void dmc520_handle_dram_ecc_errors(struct mem_ctl_info *mci, |
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bool is_ce) |
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{ |
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struct dmc520_edac *pvt = mci->pvt_info; |
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char message[DMC520_MSG_BUF_SIZE]; |
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struct ecc_error_info info; |
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u32 cnt; |
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dmc520_get_dram_ecc_error_info(pvt, is_ce, &info); |
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cnt = dmc520_get_dram_ecc_error_count(pvt, is_ce); |
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if (!cnt) |
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return; |
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snprintf(message, ARRAY_SIZE(message), |
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"rank:%d bank:%d row:%d col:%d", |
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info.rank, info.bank, |
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info.row, info.col); |
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spin_lock(&pvt->error_lock); |
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edac_mc_handle_error((is_ce ? HW_EVENT_ERR_CORRECTED : |
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HW_EVENT_ERR_UNCORRECTED), |
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mci, cnt, 0, 0, 0, info.rank, -1, -1, |
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message, ""); |
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spin_unlock(&pvt->error_lock); |
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} |
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static irqreturn_t dmc520_edac_dram_ecc_isr(int irq, struct mem_ctl_info *mci, |
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bool is_ce) |
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{ |
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struct dmc520_edac *pvt = mci->pvt_info; |
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u32 i_mask; |
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i_mask = is_ce ? DRAM_ECC_INT_CE_BIT : DRAM_ECC_INT_UE_BIT; |
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dmc520_handle_dram_ecc_errors(mci, is_ce); |
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dmc520_write_reg(pvt, i_mask, REG_OFFSET_INTERRUPT_CLR); |
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return IRQ_HANDLED; |
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} |
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static irqreturn_t dmc520_edac_dram_all_isr(int irq, struct mem_ctl_info *mci, |
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u32 irq_mask) |
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{ |
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struct dmc520_edac *pvt = mci->pvt_info; |
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irqreturn_t irq_ret = IRQ_NONE; |
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u32 status; |
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status = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_STATUS); |
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if ((irq_mask & DRAM_ECC_INT_CE_BIT) && |
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(status & DRAM_ECC_INT_CE_BIT)) |
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irq_ret = dmc520_edac_dram_ecc_isr(irq, mci, true); |
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if ((irq_mask & DRAM_ECC_INT_UE_BIT) && |
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(status & DRAM_ECC_INT_UE_BIT)) |
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irq_ret = dmc520_edac_dram_ecc_isr(irq, mci, false); |
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return irq_ret; |
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} |
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static irqreturn_t dmc520_isr(int irq, void *data) |
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{ |
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struct mem_ctl_info *mci = data; |
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struct dmc520_edac *pvt = mci->pvt_info; |
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u32 mask = 0; |
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int idx; |
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for (idx = 0; idx < NUMBER_OF_IRQS; idx++) { |
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if (pvt->irqs[idx] == irq) { |
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mask = pvt->masks[idx]; |
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break; |
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} |
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} |
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return dmc520_edac_dram_all_isr(irq, mci, mask); |
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} |
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static void dmc520_init_csrow(struct mem_ctl_info *mci) |
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{ |
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struct dmc520_edac *pvt = mci->pvt_info; |
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struct csrow_info *csi; |
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struct dimm_info *dimm; |
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u32 pages_per_rank; |
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enum dev_type dt; |
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enum mem_type mt; |
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int row, ch; |
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u64 rs; |
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dt = dmc520_get_dtype(pvt); |
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mt = dmc520_get_mtype(pvt); |
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rs = dmc520_get_rank_size(pvt); |
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pages_per_rank = rs >> PAGE_SHIFT; |
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for (row = 0; row < mci->nr_csrows; row++) { |
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csi = mci->csrows[row]; |
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for (ch = 0; ch < csi->nr_channels; ch++) { |
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dimm = csi->channels[ch]->dimm; |
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dimm->grain = pvt->mem_width_in_bytes; |
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dimm->dtype = dt; |
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dimm->mtype = mt; |
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dimm->edac_mode = EDAC_FLAG_SECDED; |
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dimm->nr_pages = pages_per_rank / csi->nr_channels; |
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} |
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} |
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} |
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static int dmc520_edac_probe(struct platform_device *pdev) |
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{ |
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bool registered[NUMBER_OF_IRQS] = { false }; |
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int irqs[NUMBER_OF_IRQS] = { -ENXIO }; |
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int masks[NUMBER_OF_IRQS] = { 0 }; |
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struct edac_mc_layer layers[1]; |
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struct dmc520_edac *pvt = NULL; |
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struct mem_ctl_info *mci; |
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void __iomem *reg_base; |
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u32 irq_mask_all = 0; |
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struct resource *res; |
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struct device *dev; |
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int ret, idx, irq; |
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u32 reg_val; |
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/* Parse the device node */ |
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dev = &pdev->dev; |
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for (idx = 0; idx < NUMBER_OF_IRQS; idx++) { |
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irq = platform_get_irq_byname(pdev, dmc520_irq_configs[idx].name); |
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irqs[idx] = irq; |
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masks[idx] = dmc520_irq_configs[idx].mask; |
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if (irq >= 0) { |
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irq_mask_all |= dmc520_irq_configs[idx].mask; |
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edac_dbg(0, "Discovered %s, irq: %d.\n", dmc520_irq_configs[idx].name, irq); |
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} |
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} |
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if (!irq_mask_all) { |
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edac_printk(KERN_ERR, EDAC_MOD_NAME, |
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"At least one valid interrupt line is expected.\n"); |
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return -EINVAL; |
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} |
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/* Initialize dmc520 edac */ |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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reg_base = devm_ioremap_resource(dev, res); |
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if (IS_ERR(reg_base)) |
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return PTR_ERR(reg_base); |
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if (!dmc520_is_ecc_enabled(reg_base)) |
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return -ENXIO; |
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layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
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layers[0].size = dmc520_get_rank_count(reg_base); |
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layers[0].is_virt_csrow = true; |
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|
|
mci = edac_mc_alloc(dmc520_mc_idx++, ARRAY_SIZE(layers), layers, sizeof(*pvt)); |
|
if (!mci) { |
|
edac_printk(KERN_ERR, EDAC_MOD_NAME, |
|
"Failed to allocate memory for mc instance\n"); |
|
ret = -ENOMEM; |
|
goto err; |
|
} |
|
|
|
pvt = mci->pvt_info; |
|
|
|
pvt->reg_base = reg_base; |
|
spin_lock_init(&pvt->error_lock); |
|
memcpy(pvt->irqs, irqs, sizeof(irqs)); |
|
memcpy(pvt->masks, masks, sizeof(masks)); |
|
|
|
platform_set_drvdata(pdev, mci); |
|
|
|
mci->pdev = dev; |
|
mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR4; |
|
mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; |
|
mci->edac_cap = EDAC_FLAG_SECDED; |
|
mci->scrub_cap = SCRUB_FLAG_HW_SRC; |
|
mci->scrub_mode = dmc520_get_scrub_type(pvt); |
|
mci->ctl_name = EDAC_CTL_NAME; |
|
mci->dev_name = dev_name(mci->pdev); |
|
mci->mod_name = EDAC_MOD_NAME; |
|
|
|
edac_op_state = EDAC_OPSTATE_INT; |
|
|
|
pvt->mem_width_in_bytes = dmc520_get_memory_width(pvt); |
|
|
|
dmc520_init_csrow(mci); |
|
|
|
/* Clear interrupts, not affecting other unrelated interrupts */ |
|
reg_val = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_CONTROL); |
|
dmc520_write_reg(pvt, reg_val & (~irq_mask_all), |
|
REG_OFFSET_INTERRUPT_CONTROL); |
|
dmc520_write_reg(pvt, irq_mask_all, REG_OFFSET_INTERRUPT_CLR); |
|
|
|
for (idx = 0; idx < NUMBER_OF_IRQS; idx++) { |
|
irq = irqs[idx]; |
|
if (irq >= 0) { |
|
ret = devm_request_irq(&pdev->dev, irq, |
|
dmc520_isr, IRQF_SHARED, |
|
dev_name(&pdev->dev), mci); |
|
if (ret < 0) { |
|
edac_printk(KERN_ERR, EDAC_MC, |
|
"Failed to request irq %d\n", irq); |
|
goto err; |
|
} |
|
registered[idx] = true; |
|
} |
|
} |
|
|
|
/* Reset DRAM CE/UE counters */ |
|
if (irq_mask_all & DRAM_ECC_INT_CE_BIT) |
|
dmc520_get_dram_ecc_error_count(pvt, true); |
|
|
|
if (irq_mask_all & DRAM_ECC_INT_UE_BIT) |
|
dmc520_get_dram_ecc_error_count(pvt, false); |
|
|
|
ret = edac_mc_add_mc(mci); |
|
if (ret) { |
|
edac_printk(KERN_ERR, EDAC_MOD_NAME, |
|
"Failed to register with EDAC core\n"); |
|
goto err; |
|
} |
|
|
|
/* Enable interrupts, not affecting other unrelated interrupts */ |
|
dmc520_write_reg(pvt, reg_val | irq_mask_all, |
|
REG_OFFSET_INTERRUPT_CONTROL); |
|
|
|
return 0; |
|
|
|
err: |
|
for (idx = 0; idx < NUMBER_OF_IRQS; idx++) { |
|
if (registered[idx]) |
|
devm_free_irq(&pdev->dev, pvt->irqs[idx], mci); |
|
} |
|
if (mci) |
|
edac_mc_free(mci); |
|
|
|
return ret; |
|
} |
|
|
|
static int dmc520_edac_remove(struct platform_device *pdev) |
|
{ |
|
u32 reg_val, idx, irq_mask_all = 0; |
|
struct mem_ctl_info *mci; |
|
struct dmc520_edac *pvt; |
|
|
|
mci = platform_get_drvdata(pdev); |
|
pvt = mci->pvt_info; |
|
|
|
/* Disable interrupts */ |
|
reg_val = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_CONTROL); |
|
dmc520_write_reg(pvt, reg_val & (~irq_mask_all), |
|
REG_OFFSET_INTERRUPT_CONTROL); |
|
|
|
/* free irq's */ |
|
for (idx = 0; idx < NUMBER_OF_IRQS; idx++) { |
|
if (pvt->irqs[idx] >= 0) { |
|
irq_mask_all |= pvt->masks[idx]; |
|
devm_free_irq(&pdev->dev, pvt->irqs[idx], mci); |
|
} |
|
} |
|
|
|
edac_mc_del_mc(&pdev->dev); |
|
edac_mc_free(mci); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id dmc520_edac_driver_id[] = { |
|
{ .compatible = "arm,dmc-520", }, |
|
{ /* end of table */ } |
|
}; |
|
|
|
MODULE_DEVICE_TABLE(of, dmc520_edac_driver_id); |
|
|
|
static struct platform_driver dmc520_edac_driver = { |
|
.driver = { |
|
.name = "dmc520", |
|
.of_match_table = dmc520_edac_driver_id, |
|
}, |
|
|
|
.probe = dmc520_edac_probe, |
|
.remove = dmc520_edac_remove |
|
}; |
|
|
|
module_platform_driver(dmc520_edac_driver); |
|
|
|
MODULE_AUTHOR("Rui Zhao <[email protected]>"); |
|
MODULE_AUTHOR("Lei Wang <[email protected]>"); |
|
MODULE_AUTHOR("Shiping Ji <[email protected]>"); |
|
MODULE_DESCRIPTION("DMC-520 ECC driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|