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306 lines
9.9 KiB
306 lines
9.9 KiB
/* |
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* drivers/dma/fsl_raid.h |
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* |
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* Freescale RAID Engine device driver |
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* |
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* Author: |
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* Harninder Rai <[email protected]> |
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* Naveen Burmi <[email protected]> |
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* |
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* Rewrite: |
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* Xuelin Shi <[email protected]> |
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* Copyright (c) 2010-2012 Freescale Semiconductor, Inc. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* * Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* * Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* * Neither the name of Freescale Semiconductor nor the |
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* names of its contributors may be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* ALTERNATIVELY, this software may be distributed under the terms of the |
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* GNU General Public License ("GPL") as published by the Free Software |
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* Foundation, either version 2 of that License or (at your option) any |
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* later version. |
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* |
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY |
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY |
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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*/ |
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#define FSL_RE_MAX_CHANS 4 |
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#define FSL_RE_DPAA_MODE BIT(30) |
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#define FSL_RE_NON_DPAA_MODE BIT(31) |
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#define FSL_RE_GFM_POLY 0x1d000000 |
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#define FSL_RE_ADD_JOB(x) ((x) << 16) |
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#define FSL_RE_RMVD_JOB(x) ((x) << 16) |
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#define FSL_RE_CFG1_CBSI 0x08000000 |
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#define FSL_RE_CFG1_CBS0 0x00080000 |
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#define FSL_RE_SLOT_FULL_SHIFT 8 |
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#define FSL_RE_SLOT_FULL(x) ((x) >> FSL_RE_SLOT_FULL_SHIFT) |
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#define FSL_RE_SLOT_AVAIL_SHIFT 8 |
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#define FSL_RE_SLOT_AVAIL(x) ((x) >> FSL_RE_SLOT_AVAIL_SHIFT) |
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#define FSL_RE_PQ_OPCODE 0x1B |
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#define FSL_RE_XOR_OPCODE 0x1A |
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#define FSL_RE_MOVE_OPCODE 0x8 |
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#define FSL_RE_FRAME_ALIGN 16 |
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#define FSL_RE_BLOCK_SIZE 0x3 /* 4096 bytes */ |
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#define FSL_RE_CACHEABLE_IO 0x0 |
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#define FSL_RE_BUFFER_OUTPUT 0x0 |
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#define FSL_RE_INTR_ON_ERROR 0x1 |
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#define FSL_RE_DATA_DEP 0x1 |
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#define FSL_RE_ENABLE_DPI 0x0 |
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#define FSL_RE_RING_SIZE 0x400 |
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#define FSL_RE_RING_SIZE_MASK (FSL_RE_RING_SIZE - 1) |
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#define FSL_RE_RING_SIZE_SHIFT 8 |
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#define FSL_RE_ADDR_BIT_SHIFT 4 |
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#define FSL_RE_ADDR_BIT_MASK (BIT(FSL_RE_ADDR_BIT_SHIFT) - 1) |
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#define FSL_RE_ERROR 0x40000000 |
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#define FSL_RE_INTR 0x80000000 |
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#define FSL_RE_CLR_INTR 0x80000000 |
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#define FSL_RE_PAUSE 0x80000000 |
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#define FSL_RE_ENABLE 0x80000000 |
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#define FSL_RE_REG_LIODN_MASK 0x00000FFF |
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#define FSL_RE_CDB_OPCODE_MASK 0xF8000000 |
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#define FSL_RE_CDB_OPCODE_SHIFT 27 |
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#define FSL_RE_CDB_EXCLEN_MASK 0x03000000 |
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#define FSL_RE_CDB_EXCLEN_SHIFT 24 |
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#define FSL_RE_CDB_EXCLQ1_MASK 0x00F00000 |
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#define FSL_RE_CDB_EXCLQ1_SHIFT 20 |
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#define FSL_RE_CDB_EXCLQ2_MASK 0x000F0000 |
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#define FSL_RE_CDB_EXCLQ2_SHIFT 16 |
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#define FSL_RE_CDB_BLKSIZE_MASK 0x0000C000 |
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#define FSL_RE_CDB_BLKSIZE_SHIFT 14 |
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#define FSL_RE_CDB_CACHE_MASK 0x00003000 |
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#define FSL_RE_CDB_CACHE_SHIFT 12 |
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#define FSL_RE_CDB_BUFFER_MASK 0x00000800 |
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#define FSL_RE_CDB_BUFFER_SHIFT 11 |
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#define FSL_RE_CDB_ERROR_MASK 0x00000400 |
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#define FSL_RE_CDB_ERROR_SHIFT 10 |
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#define FSL_RE_CDB_NRCS_MASK 0x0000003C |
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#define FSL_RE_CDB_NRCS_SHIFT 6 |
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#define FSL_RE_CDB_DEPEND_MASK 0x00000008 |
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#define FSL_RE_CDB_DEPEND_SHIFT 3 |
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#define FSL_RE_CDB_DPI_MASK 0x00000004 |
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#define FSL_RE_CDB_DPI_SHIFT 2 |
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/* |
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* the largest cf block is 19*sizeof(struct cmpnd_frame), which is 304 bytes. |
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* here 19 = 1(cdb)+2(dest)+16(src), align to 64bytes, that is 320 bytes. |
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* the largest cdb block: struct pq_cdb which is 180 bytes, adding to cf block |
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* 320+180=500, align to 64bytes, that is 512 bytes. |
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*/ |
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#define FSL_RE_CF_DESC_SIZE 320 |
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#define FSL_RE_CF_CDB_SIZE 512 |
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#define FSL_RE_CF_CDB_ALIGN 64 |
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struct fsl_re_ctrl { |
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/* General Configuration Registers */ |
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__be32 global_config; /* Global Configuration Register */ |
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u8 rsvd1[4]; |
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__be32 galois_field_config; /* Galois Field Configuration Register */ |
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u8 rsvd2[4]; |
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__be32 jq_wrr_config; /* WRR Configuration register */ |
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u8 rsvd3[4]; |
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__be32 crc_config; /* CRC Configuration register */ |
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u8 rsvd4[228]; |
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__be32 system_reset; /* System Reset Register */ |
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u8 rsvd5[252]; |
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__be32 global_status; /* Global Status Register */ |
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u8 rsvd6[832]; |
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__be32 re_liodn_base; /* LIODN Base Register */ |
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u8 rsvd7[1712]; |
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__be32 re_version_id; /* Version ID register of RE */ |
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__be32 re_version_id_2; /* Version ID 2 register of RE */ |
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u8 rsvd8[512]; |
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__be32 host_config; /* Host I/F Configuration Register */ |
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}; |
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struct fsl_re_chan_cfg { |
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/* Registers for JR interface */ |
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__be32 jr_config_0; /* Job Queue Configuration 0 Register */ |
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__be32 jr_config_1; /* Job Queue Configuration 1 Register */ |
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__be32 jr_interrupt_status; /* Job Queue Interrupt Status Register */ |
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u8 rsvd1[4]; |
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__be32 jr_command; /* Job Queue Command Register */ |
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u8 rsvd2[4]; |
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__be32 jr_status; /* Job Queue Status Register */ |
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u8 rsvd3[228]; |
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/* Input Ring */ |
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__be32 inbring_base_h; /* Inbound Ring Base Address Register - High */ |
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__be32 inbring_base_l; /* Inbound Ring Base Address Register - Low */ |
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__be32 inbring_size; /* Inbound Ring Size Register */ |
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u8 rsvd4[4]; |
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__be32 inbring_slot_avail; /* Inbound Ring Slot Available Register */ |
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u8 rsvd5[4]; |
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__be32 inbring_add_job; /* Inbound Ring Add Job Register */ |
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u8 rsvd6[4]; |
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__be32 inbring_cnsmr_indx; /* Inbound Ring Consumer Index Register */ |
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u8 rsvd7[220]; |
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/* Output Ring */ |
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__be32 oubring_base_h; /* Outbound Ring Base Address Register - High */ |
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__be32 oubring_base_l; /* Outbound Ring Base Address Register - Low */ |
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__be32 oubring_size; /* Outbound Ring Size Register */ |
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u8 rsvd8[4]; |
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__be32 oubring_job_rmvd; /* Outbound Ring Job Removed Register */ |
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u8 rsvd9[4]; |
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__be32 oubring_slot_full; /* Outbound Ring Slot Full Register */ |
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u8 rsvd10[4]; |
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__be32 oubring_prdcr_indx; /* Outbound Ring Producer Index */ |
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}; |
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/* |
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* Command Descriptor Block (CDB) for unicast move command. |
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* In RAID Engine terms, memcpy is done through move command |
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*/ |
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struct fsl_re_move_cdb { |
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__be32 cdb32; |
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}; |
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/* Data protection/integrity related fields */ |
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#define FSL_RE_DPI_APPS_MASK 0xC0000000 |
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#define FSL_RE_DPI_APPS_SHIFT 30 |
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#define FSL_RE_DPI_REF_MASK 0x30000000 |
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#define FSL_RE_DPI_REF_SHIFT 28 |
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#define FSL_RE_DPI_GUARD_MASK 0x0C000000 |
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#define FSL_RE_DPI_GUARD_SHIFT 26 |
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#define FSL_RE_DPI_ATTR_MASK 0x03000000 |
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#define FSL_RE_DPI_ATTR_SHIFT 24 |
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#define FSL_RE_DPI_META_MASK 0x0000FFFF |
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struct fsl_re_dpi { |
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__be32 dpi32; |
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__be32 ref; |
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}; |
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/* |
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* CDB for GenQ command. In RAID Engine terminology, XOR is |
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* done through this command |
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*/ |
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struct fsl_re_xor_cdb { |
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__be32 cdb32; |
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u8 gfm[16]; |
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struct fsl_re_dpi dpi_dest_spec; |
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struct fsl_re_dpi dpi_src_spec[16]; |
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}; |
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/* CDB for no-op command */ |
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struct fsl_re_noop_cdb { |
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__be32 cdb32; |
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}; |
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/* |
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* CDB for GenQQ command. In RAID Engine terminology, P/Q is |
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* done through this command |
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*/ |
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struct fsl_re_pq_cdb { |
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__be32 cdb32; |
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u8 gfm_q1[16]; |
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u8 gfm_q2[16]; |
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struct fsl_re_dpi dpi_dest_spec[2]; |
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struct fsl_re_dpi dpi_src_spec[16]; |
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}; |
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/* Compound frame */ |
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#define FSL_RE_CF_ADDR_HIGH_MASK 0x000000FF |
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#define FSL_RE_CF_EXT_MASK 0x80000000 |
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#define FSL_RE_CF_EXT_SHIFT 31 |
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#define FSL_RE_CF_FINAL_MASK 0x40000000 |
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#define FSL_RE_CF_FINAL_SHIFT 30 |
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#define FSL_RE_CF_LENGTH_MASK 0x000FFFFF |
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#define FSL_RE_CF_BPID_MASK 0x00FF0000 |
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#define FSL_RE_CF_BPID_SHIFT 16 |
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#define FSL_RE_CF_OFFSET_MASK 0x00001FFF |
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struct fsl_re_cmpnd_frame { |
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__be32 addr_high; |
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__be32 addr_low; |
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__be32 efrl32; |
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__be32 rbro32; |
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}; |
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/* Frame descriptor */ |
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#define FSL_RE_HWDESC_LIODN_MASK 0x3F000000 |
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#define FSL_RE_HWDESC_LIODN_SHIFT 24 |
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#define FSL_RE_HWDESC_BPID_MASK 0x00FF0000 |
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#define FSL_RE_HWDESC_BPID_SHIFT 16 |
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#define FSL_RE_HWDESC_ELIODN_MASK 0x0000F000 |
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#define FSL_RE_HWDESC_ELIODN_SHIFT 12 |
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#define FSL_RE_HWDESC_FMT_SHIFT 29 |
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#define FSL_RE_HWDESC_FMT_MASK (0x3 << FSL_RE_HWDESC_FMT_SHIFT) |
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struct fsl_re_hw_desc { |
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__be32 lbea32; |
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__be32 addr_low; |
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__be32 fmt32; |
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__be32 status; |
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}; |
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/* Raid Engine device private data */ |
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struct fsl_re_drv_private { |
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u8 total_chans; |
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struct dma_device dma_dev; |
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struct fsl_re_ctrl *re_regs; |
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struct fsl_re_chan *re_jrs[FSL_RE_MAX_CHANS]; |
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struct dma_pool *cf_desc_pool; |
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struct dma_pool *hw_desc_pool; |
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}; |
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/* Per job ring data structure */ |
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struct fsl_re_chan { |
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char name[16]; |
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spinlock_t desc_lock; /* queue lock */ |
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struct list_head ack_q; /* wait to acked queue */ |
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struct list_head active_q; /* already issued on hw, not completed */ |
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struct list_head submit_q; |
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struct list_head free_q; /* alloc available queue */ |
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struct device *dev; |
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struct fsl_re_drv_private *re_dev; |
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struct dma_chan chan; |
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struct fsl_re_chan_cfg *jrregs; |
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int irq; |
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struct tasklet_struct irqtask; |
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u32 alloc_count; |
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/* hw descriptor ring for inbound queue*/ |
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dma_addr_t inb_phys_addr; |
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struct fsl_re_hw_desc *inb_ring_virt_addr; |
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u32 inb_count; |
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/* hw descriptor ring for outbound queue */ |
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dma_addr_t oub_phys_addr; |
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struct fsl_re_hw_desc *oub_ring_virt_addr; |
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u32 oub_count; |
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}; |
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/* Async transaction descriptor */ |
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struct fsl_re_desc { |
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struct dma_async_tx_descriptor async_tx; |
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struct list_head node; |
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struct fsl_re_hw_desc hwdesc; |
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struct fsl_re_chan *re_chan; |
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/* hwdesc will point to cf_addr */ |
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void *cf_addr; |
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dma_addr_t cf_paddr; |
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void *cdb_addr; |
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dma_addr_t cdb_paddr; |
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int status; |
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};
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