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289 lines
7.5 KiB
289 lines
7.5 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/** |
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* SHA-512 routines supporting the Power 7+ Nest Accelerators driver |
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* |
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* Copyright (C) 2011-2012 International Business Machines Inc. |
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* |
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* Author: Kent Yoder <[email protected]> |
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*/ |
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#include <crypto/internal/hash.h> |
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#include <crypto/sha2.h> |
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#include <linux/module.h> |
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#include <asm/vio.h> |
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#include "nx_csbcpb.h" |
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#include "nx.h" |
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static int nx_crypto_ctx_sha512_init(struct crypto_tfm *tfm) |
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{ |
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struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(tfm); |
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int err; |
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err = nx_crypto_ctx_sha_init(tfm); |
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if (err) |
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return err; |
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nx_ctx_init(nx_ctx, HCOP_FC_SHA); |
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nx_ctx->ap = &nx_ctx->props[NX_PROPS_SHA512]; |
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NX_CPB_SET_DIGEST_SIZE(nx_ctx->csbcpb, NX_DS_SHA512); |
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return 0; |
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} |
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static int nx_sha512_init(struct shash_desc *desc) |
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{ |
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struct sha512_state *sctx = shash_desc_ctx(desc); |
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memset(sctx, 0, sizeof *sctx); |
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sctx->state[0] = __cpu_to_be64(SHA512_H0); |
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sctx->state[1] = __cpu_to_be64(SHA512_H1); |
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sctx->state[2] = __cpu_to_be64(SHA512_H2); |
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sctx->state[3] = __cpu_to_be64(SHA512_H3); |
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sctx->state[4] = __cpu_to_be64(SHA512_H4); |
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sctx->state[5] = __cpu_to_be64(SHA512_H5); |
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sctx->state[6] = __cpu_to_be64(SHA512_H6); |
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sctx->state[7] = __cpu_to_be64(SHA512_H7); |
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sctx->count[0] = 0; |
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return 0; |
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} |
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static int nx_sha512_update(struct shash_desc *desc, const u8 *data, |
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unsigned int len) |
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{ |
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struct sha512_state *sctx = shash_desc_ctx(desc); |
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struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base); |
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struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb; |
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struct nx_sg *out_sg; |
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u64 to_process, leftover = 0, total; |
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unsigned long irq_flags; |
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int rc = 0; |
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int data_len; |
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u32 max_sg_len; |
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u64 buf_len = (sctx->count[0] % SHA512_BLOCK_SIZE); |
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spin_lock_irqsave(&nx_ctx->lock, irq_flags); |
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/* 2 cases for total data len: |
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* 1: < SHA512_BLOCK_SIZE: copy into state, return 0 |
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* 2: >= SHA512_BLOCK_SIZE: process X blocks, copy in leftover |
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*/ |
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total = (sctx->count[0] % SHA512_BLOCK_SIZE) + len; |
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if (total < SHA512_BLOCK_SIZE) { |
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memcpy(sctx->buf + buf_len, data, len); |
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sctx->count[0] += len; |
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goto out; |
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} |
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memcpy(csbcpb->cpb.sha512.message_digest, sctx->state, SHA512_DIGEST_SIZE); |
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NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE; |
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NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION; |
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max_sg_len = min_t(u64, nx_ctx->ap->sglen, |
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nx_driver.of.max_sg_len/sizeof(struct nx_sg)); |
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max_sg_len = min_t(u64, max_sg_len, |
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nx_ctx->ap->databytelen/NX_PAGE_SIZE); |
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data_len = SHA512_DIGEST_SIZE; |
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out_sg = nx_build_sg_list(nx_ctx->out_sg, (u8 *)sctx->state, |
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&data_len, max_sg_len); |
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nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg); |
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if (data_len != SHA512_DIGEST_SIZE) { |
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rc = -EINVAL; |
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goto out; |
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} |
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do { |
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int used_sgs = 0; |
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struct nx_sg *in_sg = nx_ctx->in_sg; |
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if (buf_len) { |
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data_len = buf_len; |
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in_sg = nx_build_sg_list(in_sg, |
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(u8 *) sctx->buf, |
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&data_len, max_sg_len); |
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if (data_len != buf_len) { |
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rc = -EINVAL; |
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goto out; |
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} |
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used_sgs = in_sg - nx_ctx->in_sg; |
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} |
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/* to_process: SHA512_BLOCK_SIZE aligned chunk to be |
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* processed in this iteration. This value is restricted |
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* by sg list limits and number of sgs we already used |
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* for leftover data. (see above) |
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* In ideal case, we could allow NX_PAGE_SIZE * max_sg_len, |
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* but because data may not be aligned, we need to account |
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* for that too. */ |
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to_process = min_t(u64, total, |
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(max_sg_len - 1 - used_sgs) * NX_PAGE_SIZE); |
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to_process = to_process & ~(SHA512_BLOCK_SIZE - 1); |
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data_len = to_process - buf_len; |
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in_sg = nx_build_sg_list(in_sg, (u8 *) data, |
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&data_len, max_sg_len); |
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nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg); |
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if (data_len != (to_process - buf_len)) { |
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rc = -EINVAL; |
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goto out; |
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} |
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to_process = data_len + buf_len; |
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leftover = total - to_process; |
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/* |
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* we've hit the nx chip previously and we're updating |
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* again, so copy over the partial digest. |
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*/ |
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memcpy(csbcpb->cpb.sha512.input_partial_digest, |
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csbcpb->cpb.sha512.message_digest, |
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SHA512_DIGEST_SIZE); |
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if (!nx_ctx->op.inlen || !nx_ctx->op.outlen) { |
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rc = -EINVAL; |
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goto out; |
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} |
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rc = nx_hcall_sync(nx_ctx, &nx_ctx->op, 0); |
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if (rc) |
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goto out; |
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atomic_inc(&(nx_ctx->stats->sha512_ops)); |
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total -= to_process; |
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data += to_process - buf_len; |
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buf_len = 0; |
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} while (leftover >= SHA512_BLOCK_SIZE); |
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/* copy the leftover back into the state struct */ |
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if (leftover) |
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memcpy(sctx->buf, data, leftover); |
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sctx->count[0] += len; |
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memcpy(sctx->state, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE); |
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out: |
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spin_unlock_irqrestore(&nx_ctx->lock, irq_flags); |
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return rc; |
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} |
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static int nx_sha512_final(struct shash_desc *desc, u8 *out) |
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{ |
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struct sha512_state *sctx = shash_desc_ctx(desc); |
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struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base); |
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struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb; |
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struct nx_sg *in_sg, *out_sg; |
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u32 max_sg_len; |
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u64 count0; |
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unsigned long irq_flags; |
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int rc = 0; |
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int len; |
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spin_lock_irqsave(&nx_ctx->lock, irq_flags); |
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max_sg_len = min_t(u64, nx_ctx->ap->sglen, |
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nx_driver.of.max_sg_len/sizeof(struct nx_sg)); |
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max_sg_len = min_t(u64, max_sg_len, |
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nx_ctx->ap->databytelen/NX_PAGE_SIZE); |
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/* final is represented by continuing the operation and indicating that |
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* this is not an intermediate operation */ |
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if (sctx->count[0] >= SHA512_BLOCK_SIZE) { |
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/* we've hit the nx chip previously, now we're finalizing, |
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* so copy over the partial digest */ |
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memcpy(csbcpb->cpb.sha512.input_partial_digest, sctx->state, |
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SHA512_DIGEST_SIZE); |
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NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE; |
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NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION; |
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} else { |
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NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE; |
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NX_CPB_FDM(csbcpb) &= ~NX_FDM_CONTINUATION; |
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} |
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NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE; |
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count0 = sctx->count[0] * 8; |
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csbcpb->cpb.sha512.message_bit_length_lo = count0; |
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len = sctx->count[0] & (SHA512_BLOCK_SIZE - 1); |
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in_sg = nx_build_sg_list(nx_ctx->in_sg, sctx->buf, &len, |
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max_sg_len); |
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if (len != (sctx->count[0] & (SHA512_BLOCK_SIZE - 1))) { |
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rc = -EINVAL; |
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goto out; |
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} |
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len = SHA512_DIGEST_SIZE; |
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out_sg = nx_build_sg_list(nx_ctx->out_sg, out, &len, |
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max_sg_len); |
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nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg); |
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nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg); |
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if (!nx_ctx->op.outlen) { |
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rc = -EINVAL; |
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goto out; |
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} |
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rc = nx_hcall_sync(nx_ctx, &nx_ctx->op, 0); |
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if (rc) |
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goto out; |
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atomic_inc(&(nx_ctx->stats->sha512_ops)); |
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atomic64_add(sctx->count[0], &(nx_ctx->stats->sha512_bytes)); |
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memcpy(out, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE); |
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out: |
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spin_unlock_irqrestore(&nx_ctx->lock, irq_flags); |
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return rc; |
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} |
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static int nx_sha512_export(struct shash_desc *desc, void *out) |
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{ |
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struct sha512_state *sctx = shash_desc_ctx(desc); |
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memcpy(out, sctx, sizeof(*sctx)); |
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return 0; |
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} |
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static int nx_sha512_import(struct shash_desc *desc, const void *in) |
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{ |
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struct sha512_state *sctx = shash_desc_ctx(desc); |
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memcpy(sctx, in, sizeof(*sctx)); |
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return 0; |
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} |
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struct shash_alg nx_shash_sha512_alg = { |
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.digestsize = SHA512_DIGEST_SIZE, |
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.init = nx_sha512_init, |
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.update = nx_sha512_update, |
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.final = nx_sha512_final, |
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.export = nx_sha512_export, |
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.import = nx_sha512_import, |
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.descsize = sizeof(struct sha512_state), |
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.statesize = sizeof(struct sha512_state), |
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.base = { |
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.cra_name = "sha512", |
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.cra_driver_name = "sha512-nx", |
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.cra_priority = 300, |
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.cra_blocksize = SHA512_BLOCK_SIZE, |
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.cra_module = THIS_MODULE, |
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.cra_ctxsize = sizeof(struct nx_crypto_ctx), |
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.cra_init = nx_crypto_ctx_sha512_init, |
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.cra_exit = nx_crypto_ctx_exit, |
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} |
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};
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