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648 lines
16 KiB
648 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2006-2008 Simtec Electronics |
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* http://armlinux.simtec.co.uk/ |
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* Ben Dooks <[email protected]> |
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* |
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* S3C24XX CPU Frequency scaling |
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*/ |
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|
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <linux/init.h> |
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#include <linux/module.h> |
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#include <linux/interrupt.h> |
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#include <linux/ioport.h> |
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#include <linux/cpufreq.h> |
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#include <linux/cpu.h> |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/device.h> |
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#include <linux/sysfs.h> |
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#include <linux/slab.h> |
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#include <linux/soc/samsung/s3c-cpufreq-core.h> |
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#include <linux/soc/samsung/s3c-pm.h> |
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#include <asm/mach/arch.h> |
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#include <asm/mach/map.h> |
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/* note, cpufreq support deals in kHz, no Hz */ |
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static struct cpufreq_driver s3c24xx_driver; |
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static struct s3c_cpufreq_config cpu_cur; |
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static struct s3c_iotimings s3c24xx_iotiming; |
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static struct cpufreq_frequency_table *pll_reg; |
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static unsigned int last_target = ~0; |
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static unsigned int ftab_size; |
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static struct cpufreq_frequency_table *ftab; |
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static struct clk *_clk_mpll; |
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static struct clk *_clk_xtal; |
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static struct clk *clk_fclk; |
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static struct clk *clk_hclk; |
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static struct clk *clk_pclk; |
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static struct clk *clk_arm; |
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#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS |
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struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void) |
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{ |
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return &cpu_cur; |
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} |
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struct s3c_iotimings *s3c_cpufreq_getiotimings(void) |
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{ |
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return &s3c24xx_iotiming; |
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} |
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#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS */ |
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static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg) |
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{ |
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unsigned long fclk, pclk, hclk, armclk; |
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cfg->freq.fclk = fclk = clk_get_rate(clk_fclk); |
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cfg->freq.hclk = hclk = clk_get_rate(clk_hclk); |
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cfg->freq.pclk = pclk = clk_get_rate(clk_pclk); |
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cfg->freq.armclk = armclk = clk_get_rate(clk_arm); |
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cfg->pll.driver_data = s3c24xx_read_mpllcon(); |
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cfg->pll.frequency = fclk; |
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cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); |
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cfg->divs.h_divisor = fclk / hclk; |
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cfg->divs.p_divisor = fclk / pclk; |
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} |
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static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg) |
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{ |
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unsigned long pll = cfg->pll.frequency; |
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cfg->freq.fclk = pll; |
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cfg->freq.hclk = pll / cfg->divs.h_divisor; |
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cfg->freq.pclk = pll / cfg->divs.p_divisor; |
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/* convert hclk into 10ths of nanoseconds for io calcs */ |
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cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); |
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} |
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static inline int closer(unsigned int target, unsigned int n, unsigned int c) |
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{ |
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int diff_cur = abs(target - c); |
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int diff_new = abs(target - n); |
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return (diff_new < diff_cur); |
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} |
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static void s3c_cpufreq_show(const char *pfx, |
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struct s3c_cpufreq_config *cfg) |
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{ |
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s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n", |
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pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk, |
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cfg->freq.hclk, cfg->divs.h_divisor, |
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cfg->freq.pclk, cfg->divs.p_divisor); |
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} |
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/* functions to wrapper the driver info calls to do the cpu specific work */ |
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static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg) |
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{ |
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if (cfg->info->set_iotiming) |
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(cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming); |
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} |
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static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg) |
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{ |
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if (cfg->info->calc_iotiming) |
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return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming); |
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return 0; |
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} |
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static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) |
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{ |
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(cfg->info->set_refresh)(cfg); |
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} |
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static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) |
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{ |
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(cfg->info->set_divs)(cfg); |
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} |
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static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) |
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{ |
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return (cfg->info->calc_divs)(cfg); |
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} |
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static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg) |
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{ |
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cfg->mpll = _clk_mpll; |
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(cfg->info->set_fvco)(cfg); |
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} |
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static inline void s3c_cpufreq_updateclk(struct clk *clk, |
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unsigned int freq) |
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{ |
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clk_set_rate(clk, freq); |
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} |
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static int s3c_cpufreq_settarget(struct cpufreq_policy *policy, |
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unsigned int target_freq, |
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struct cpufreq_frequency_table *pll) |
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{ |
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struct s3c_cpufreq_freqs freqs; |
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struct s3c_cpufreq_config cpu_new; |
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unsigned long flags; |
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cpu_new = cpu_cur; /* copy new from current */ |
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s3c_cpufreq_show("cur", &cpu_cur); |
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/* TODO - check for DMA currently outstanding */ |
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cpu_new.pll = pll ? *pll : cpu_cur.pll; |
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if (pll) |
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freqs.pll_changing = 1; |
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/* update our frequencies */ |
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cpu_new.freq.armclk = target_freq; |
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cpu_new.freq.fclk = cpu_new.pll.frequency; |
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if (s3c_cpufreq_calcdivs(&cpu_new) < 0) { |
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pr_err("no divisors for %d\n", target_freq); |
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goto err_notpossible; |
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} |
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s3c_freq_dbg("%s: got divs\n", __func__); |
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s3c_cpufreq_calc(&cpu_new); |
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s3c_freq_dbg("%s: calculated frequencies for new\n", __func__); |
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if (cpu_new.freq.hclk != cpu_cur.freq.hclk) { |
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if (s3c_cpufreq_calcio(&cpu_new) < 0) { |
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pr_err("%s: no IO timings\n", __func__); |
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goto err_notpossible; |
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} |
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} |
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s3c_cpufreq_show("new", &cpu_new); |
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/* setup our cpufreq parameters */ |
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freqs.old = cpu_cur.freq; |
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freqs.new = cpu_new.freq; |
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freqs.freqs.old = cpu_cur.freq.armclk / 1000; |
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freqs.freqs.new = cpu_new.freq.armclk / 1000; |
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/* update f/h/p clock settings before we issue the change |
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* notification, so that drivers do not need to do anything |
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* special if they want to recalculate on CPUFREQ_PRECHANGE. */ |
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s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency); |
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s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk); |
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s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk); |
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s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk); |
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/* start the frequency change */ |
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cpufreq_freq_transition_begin(policy, &freqs.freqs); |
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/* If hclk is staying the same, then we do not need to |
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* re-write the IO or the refresh timings whilst we are changing |
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* speed. */ |
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local_irq_save(flags); |
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/* is our memory clock slowing down? */ |
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if (cpu_new.freq.hclk < cpu_cur.freq.hclk) { |
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s3c_cpufreq_setrefresh(&cpu_new); |
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s3c_cpufreq_setio(&cpu_new); |
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} |
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if (cpu_new.freq.fclk == cpu_cur.freq.fclk) { |
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/* not changing PLL, just set the divisors */ |
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s3c_cpufreq_setdivs(&cpu_new); |
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} else { |
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if (cpu_new.freq.fclk < cpu_cur.freq.fclk) { |
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/* slow the cpu down, then set divisors */ |
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s3c_cpufreq_setfvco(&cpu_new); |
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s3c_cpufreq_setdivs(&cpu_new); |
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} else { |
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/* set the divisors, then speed up */ |
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s3c_cpufreq_setdivs(&cpu_new); |
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s3c_cpufreq_setfvco(&cpu_new); |
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} |
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} |
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/* did our memory clock speed up */ |
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if (cpu_new.freq.hclk > cpu_cur.freq.hclk) { |
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s3c_cpufreq_setrefresh(&cpu_new); |
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s3c_cpufreq_setio(&cpu_new); |
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} |
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/* update our current settings */ |
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cpu_cur = cpu_new; |
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local_irq_restore(flags); |
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/* notify everyone we've done this */ |
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cpufreq_freq_transition_end(policy, &freqs.freqs, 0); |
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s3c_freq_dbg("%s: finished\n", __func__); |
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return 0; |
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err_notpossible: |
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pr_err("no compatible settings for %d\n", target_freq); |
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return -EINVAL; |
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} |
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/* s3c_cpufreq_target |
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* |
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* called by the cpufreq core to adjust the frequency that the CPU |
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* is currently running at. |
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*/ |
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static int s3c_cpufreq_target(struct cpufreq_policy *policy, |
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unsigned int target_freq, |
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unsigned int relation) |
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{ |
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struct cpufreq_frequency_table *pll; |
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unsigned int index; |
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/* avoid repeated calls which cause a needless amout of duplicated |
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* logging output (and CPU time as the calculation process is |
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* done) */ |
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if (target_freq == last_target) |
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return 0; |
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last_target = target_freq; |
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s3c_freq_dbg("%s: policy %p, target %u, relation %u\n", |
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__func__, policy, target_freq, relation); |
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if (ftab) { |
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index = cpufreq_frequency_table_target(policy, target_freq, |
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relation); |
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s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__, |
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target_freq, index, ftab[index].frequency); |
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target_freq = ftab[index].frequency; |
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} |
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target_freq *= 1000; /* convert target to Hz */ |
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/* find the settings for our new frequency */ |
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if (!pll_reg || cpu_cur.lock_pll) { |
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/* either we've not got any PLL values, or we've locked |
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* to the current one. */ |
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pll = NULL; |
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} else { |
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struct cpufreq_policy tmp_policy; |
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/* we keep the cpu pll table in Hz, to ensure we get an |
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* accurate value for the PLL output. */ |
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tmp_policy.min = policy->min * 1000; |
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tmp_policy.max = policy->max * 1000; |
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tmp_policy.cpu = policy->cpu; |
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tmp_policy.freq_table = pll_reg; |
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/* cpufreq_frequency_table_target returns the index |
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* of the table entry, not the value of |
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* the table entry's index field. */ |
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index = cpufreq_frequency_table_target(&tmp_policy, target_freq, |
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relation); |
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pll = pll_reg + index; |
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s3c_freq_dbg("%s: target %u => %u\n", |
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__func__, target_freq, pll->frequency); |
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target_freq = pll->frequency; |
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} |
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return s3c_cpufreq_settarget(policy, target_freq, pll); |
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} |
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struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name) |
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{ |
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struct clk *clk; |
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clk = clk_get(dev, name); |
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if (IS_ERR(clk)) |
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pr_err("failed to get clock '%s'\n", name); |
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return clk; |
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} |
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static int s3c_cpufreq_init(struct cpufreq_policy *policy) |
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{ |
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policy->clk = clk_arm; |
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policy->cpuinfo.transition_latency = cpu_cur.info->latency; |
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policy->freq_table = ftab; |
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return 0; |
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} |
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static int __init s3c_cpufreq_initclks(void) |
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{ |
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_clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll"); |
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_clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal"); |
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clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk"); |
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clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk"); |
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clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk"); |
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clk_arm = s3c_cpufreq_clk_get(NULL, "armclk"); |
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if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) || |
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IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) { |
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pr_err("%s: could not get clock(s)\n", __func__); |
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return -ENOENT; |
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} |
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pr_info("%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n", |
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__func__, |
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clk_get_rate(clk_fclk) / 1000, |
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clk_get_rate(clk_hclk) / 1000, |
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clk_get_rate(clk_pclk) / 1000, |
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clk_get_rate(clk_arm) / 1000); |
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return 0; |
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} |
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#ifdef CONFIG_PM |
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static struct cpufreq_frequency_table suspend_pll; |
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static unsigned int suspend_freq; |
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static int s3c_cpufreq_suspend(struct cpufreq_policy *policy) |
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{ |
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suspend_pll.frequency = clk_get_rate(_clk_mpll); |
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suspend_pll.driver_data = s3c24xx_read_mpllcon(); |
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suspend_freq = clk_get_rate(clk_arm); |
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return 0; |
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} |
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static int s3c_cpufreq_resume(struct cpufreq_policy *policy) |
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{ |
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int ret; |
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s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy); |
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last_target = ~0; /* invalidate last_target setting */ |
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/* whilst we will be called later on, we try and re-set the |
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* cpu frequencies as soon as possible so that we do not end |
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* up resuming devices and then immediately having to re-set |
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* a number of settings once these devices have restarted. |
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* |
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* as a note, it is expected devices are not used until they |
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* have been un-suspended and at that time they should have |
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* used the updated clock settings. |
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*/ |
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ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll); |
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if (ret) { |
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pr_err("%s: failed to reset pll/freq\n", __func__); |
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return ret; |
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} |
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return 0; |
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} |
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#else |
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#define s3c_cpufreq_resume NULL |
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#define s3c_cpufreq_suspend NULL |
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#endif |
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static struct cpufreq_driver s3c24xx_driver = { |
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.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
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.target = s3c_cpufreq_target, |
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.get = cpufreq_generic_get, |
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.init = s3c_cpufreq_init, |
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.suspend = s3c_cpufreq_suspend, |
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.resume = s3c_cpufreq_resume, |
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.name = "s3c24xx", |
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}; |
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int s3c_cpufreq_register(struct s3c_cpufreq_info *info) |
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{ |
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if (!info || !info->name) { |
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pr_err("%s: failed to pass valid information\n", __func__); |
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return -EINVAL; |
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} |
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pr_info("S3C24XX CPU Frequency driver, %s cpu support\n", |
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info->name); |
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/* check our driver info has valid data */ |
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BUG_ON(info->set_refresh == NULL); |
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BUG_ON(info->set_divs == NULL); |
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BUG_ON(info->calc_divs == NULL); |
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/* info->set_fvco is optional, depending on whether there |
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* is a need to set the clock code. */ |
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cpu_cur.info = info; |
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/* Note, driver registering should probably update locktime */ |
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return 0; |
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} |
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int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board) |
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{ |
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struct s3c_cpufreq_board *ours; |
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if (!board) { |
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pr_info("%s: no board data\n", __func__); |
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return -EINVAL; |
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} |
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/* Copy the board information so that each board can make this |
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* initdata. */ |
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ours = kzalloc(sizeof(*ours), GFP_KERNEL); |
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if (!ours) |
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return -ENOMEM; |
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*ours = *board; |
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cpu_cur.board = ours; |
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return 0; |
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} |
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static int __init s3c_cpufreq_auto_io(void) |
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{ |
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int ret; |
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if (!cpu_cur.info->get_iotiming) { |
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pr_err("%s: get_iotiming undefined\n", __func__); |
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return -ENOENT; |
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} |
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pr_info("%s: working out IO settings\n", __func__); |
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ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming); |
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if (ret) |
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pr_err("%s: failed to get timings\n", __func__); |
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return ret; |
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} |
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/* if one or is zero, then return the other, otherwise return the min */ |
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#define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b)) |
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/** |
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* s3c_cpufreq_freq_min - find the minimum settings for the given freq. |
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* @dst: The destination structure |
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* @a: One argument. |
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* @b: The other argument. |
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* |
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* Create a minimum of each frequency entry in the 'struct s3c_freq', |
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* unless the entry is zero when it is ignored and the non-zero argument |
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* used. |
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*/ |
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static void s3c_cpufreq_freq_min(struct s3c_freq *dst, |
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struct s3c_freq *a, struct s3c_freq *b) |
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{ |
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dst->fclk = do_min(a->fclk, b->fclk); |
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dst->hclk = do_min(a->hclk, b->hclk); |
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dst->pclk = do_min(a->pclk, b->pclk); |
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dst->armclk = do_min(a->armclk, b->armclk); |
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} |
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static inline u32 calc_locktime(u32 freq, u32 time_us) |
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{ |
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u32 result; |
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result = freq * time_us; |
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result = DIV_ROUND_UP(result, 1000 * 1000); |
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return result; |
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} |
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static void s3c_cpufreq_update_loctkime(void) |
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{ |
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unsigned int bits = cpu_cur.info->locktime_bits; |
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u32 rate = (u32)clk_get_rate(_clk_xtal); |
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u32 val; |
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if (bits == 0) { |
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WARN_ON(1); |
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return; |
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} |
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val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits; |
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val |= calc_locktime(rate, cpu_cur.info->locktime_m); |
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pr_info("%s: new locktime is 0x%08x\n", __func__, val); |
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s3c24xx_write_locktime(val); |
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} |
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static int s3c_cpufreq_build_freq(void) |
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{ |
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int size, ret; |
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kfree(ftab); |
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|
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size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0); |
|
size++; |
|
|
|
ftab = kcalloc(size, sizeof(*ftab), GFP_KERNEL); |
|
if (!ftab) |
|
return -ENOMEM; |
|
|
|
ftab_size = size; |
|
|
|
ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size); |
|
s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END); |
|
|
|
return 0; |
|
} |
|
|
|
static int __init s3c_cpufreq_initcall(void) |
|
{ |
|
int ret = 0; |
|
|
|
if (cpu_cur.info && cpu_cur.board) { |
|
ret = s3c_cpufreq_initclks(); |
|
if (ret) |
|
goto out; |
|
|
|
/* get current settings */ |
|
s3c_cpufreq_getcur(&cpu_cur); |
|
s3c_cpufreq_show("cur", &cpu_cur); |
|
|
|
if (cpu_cur.board->auto_io) { |
|
ret = s3c_cpufreq_auto_io(); |
|
if (ret) { |
|
pr_err("%s: failed to get io timing\n", |
|
__func__); |
|
goto out; |
|
} |
|
} |
|
|
|
if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) { |
|
pr_err("%s: no IO support registered\n", __func__); |
|
ret = -EINVAL; |
|
goto out; |
|
} |
|
|
|
if (!cpu_cur.info->need_pll) |
|
cpu_cur.lock_pll = 1; |
|
|
|
s3c_cpufreq_update_loctkime(); |
|
|
|
s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max, |
|
&cpu_cur.info->max); |
|
|
|
if (cpu_cur.info->calc_freqtable) |
|
s3c_cpufreq_build_freq(); |
|
|
|
ret = cpufreq_register_driver(&s3c24xx_driver); |
|
} |
|
|
|
out: |
|
return ret; |
|
} |
|
|
|
late_initcall(s3c_cpufreq_initcall); |
|
|
|
/** |
|
* s3c_plltab_register - register CPU PLL table. |
|
* @plls: The list of PLL entries. |
|
* @plls_no: The size of the PLL entries @plls. |
|
* |
|
* Register the given set of PLLs with the system. |
|
*/ |
|
int s3c_plltab_register(struct cpufreq_frequency_table *plls, |
|
unsigned int plls_no) |
|
{ |
|
struct cpufreq_frequency_table *vals; |
|
unsigned int size; |
|
|
|
size = sizeof(*vals) * (plls_no + 1); |
|
|
|
vals = kzalloc(size, GFP_KERNEL); |
|
if (vals) { |
|
memcpy(vals, plls, size); |
|
pll_reg = vals; |
|
|
|
/* write a terminating entry, we don't store it in the |
|
* table that is stored in the kernel */ |
|
vals += plls_no; |
|
vals->frequency = CPUFREQ_TABLE_END; |
|
|
|
pr_info("%d PLL entries\n", plls_no); |
|
} else |
|
pr_err("no memory for PLL tables\n"); |
|
|
|
return vals ? 0 : -ENOMEM; |
|
}
|
|
|