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508 lines
14 KiB
508 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* 64-bit Periodic Interval Timer driver |
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* |
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* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries |
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* |
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* Author: Claudiu Beznea <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/clockchips.h> |
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#include <linux/interrupt.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/sched_clock.h> |
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#include <linux/slab.h> |
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#define MCHP_PIT64B_CR 0x00 /* Control Register */ |
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#define MCHP_PIT64B_CR_START BIT(0) |
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#define MCHP_PIT64B_CR_SWRST BIT(8) |
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#define MCHP_PIT64B_MR 0x04 /* Mode Register */ |
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#define MCHP_PIT64B_MR_CONT BIT(0) |
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#define MCHP_PIT64B_MR_ONE_SHOT (0) |
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#define MCHP_PIT64B_MR_SGCLK BIT(3) |
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#define MCHP_PIT64B_MR_PRES GENMASK(11, 8) |
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#define MCHP_PIT64B_LSB_PR 0x08 /* LSB Period Register */ |
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#define MCHP_PIT64B_MSB_PR 0x0C /* MSB Period Register */ |
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#define MCHP_PIT64B_IER 0x10 /* Interrupt Enable Register */ |
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#define MCHP_PIT64B_IER_PERIOD BIT(0) |
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#define MCHP_PIT64B_ISR 0x1C /* Interrupt Status Register */ |
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#define MCHP_PIT64B_TLSBR 0x20 /* Timer LSB Register */ |
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#define MCHP_PIT64B_TMSBR 0x24 /* Timer MSB Register */ |
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#define MCHP_PIT64B_PRES_MAX 0x10 |
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#define MCHP_PIT64B_LSBMASK GENMASK_ULL(31, 0) |
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#define MCHP_PIT64B_PRES_TO_MODE(p) (MCHP_PIT64B_MR_PRES & ((p) << 8)) |
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#define MCHP_PIT64B_MODE_TO_PRES(m) ((MCHP_PIT64B_MR_PRES & (m)) >> 8) |
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#define MCHP_PIT64B_DEF_CS_FREQ 5000000UL /* 5 MHz */ |
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#define MCHP_PIT64B_DEF_CE_FREQ 32768 /* 32 KHz */ |
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#define MCHP_PIT64B_NAME "pit64b" |
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/** |
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* struct mchp_pit64b_timer - PIT64B timer data structure |
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* @base: base address of PIT64B hardware block |
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* @pclk: PIT64B's peripheral clock |
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* @gclk: PIT64B's generic clock |
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* @mode: precomputed value for mode register |
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*/ |
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struct mchp_pit64b_timer { |
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void __iomem *base; |
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struct clk *pclk; |
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struct clk *gclk; |
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u32 mode; |
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}; |
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/** |
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* mchp_pit64b_clkevt - PIT64B clockevent data structure |
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* @timer: PIT64B timer |
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* @clkevt: clockevent |
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*/ |
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struct mchp_pit64b_clkevt { |
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struct mchp_pit64b_timer timer; |
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struct clock_event_device clkevt; |
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}; |
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#define clkevt_to_mchp_pit64b_timer(x) \ |
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((struct mchp_pit64b_timer *)container_of(x,\ |
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struct mchp_pit64b_clkevt, clkevt)) |
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/** |
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* mchp_pit64b_clksrc - PIT64B clocksource data structure |
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* @timer: PIT64B timer |
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* @clksrc: clocksource |
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*/ |
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struct mchp_pit64b_clksrc { |
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struct mchp_pit64b_timer timer; |
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struct clocksource clksrc; |
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}; |
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#define clksrc_to_mchp_pit64b_timer(x) \ |
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((struct mchp_pit64b_timer *)container_of(x,\ |
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struct mchp_pit64b_clksrc, clksrc)) |
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/* Base address for clocksource timer. */ |
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static void __iomem *mchp_pit64b_cs_base; |
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/* Default cycles for clockevent timer. */ |
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static u64 mchp_pit64b_ce_cycles; |
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static inline u64 mchp_pit64b_cnt_read(void __iomem *base) |
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{ |
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unsigned long flags; |
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u32 low, high; |
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raw_local_irq_save(flags); |
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/* |
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* When using a 64 bit period TLSB must be read first, followed by the |
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* read of TMSB. This sequence generates an atomic read of the 64 bit |
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* timer value whatever the lapse of time between the accesses. |
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*/ |
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low = readl_relaxed(base + MCHP_PIT64B_TLSBR); |
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high = readl_relaxed(base + MCHP_PIT64B_TMSBR); |
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raw_local_irq_restore(flags); |
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return (((u64)high << 32) | low); |
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} |
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static inline void mchp_pit64b_reset(struct mchp_pit64b_timer *timer, |
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u64 cycles, u32 mode, u32 irqs) |
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{ |
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u32 low, high; |
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low = cycles & MCHP_PIT64B_LSBMASK; |
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high = cycles >> 32; |
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writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); |
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writel_relaxed(mode | timer->mode, timer->base + MCHP_PIT64B_MR); |
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writel_relaxed(high, timer->base + MCHP_PIT64B_MSB_PR); |
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writel_relaxed(low, timer->base + MCHP_PIT64B_LSB_PR); |
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writel_relaxed(irqs, timer->base + MCHP_PIT64B_IER); |
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writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR); |
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} |
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static void mchp_pit64b_suspend(struct mchp_pit64b_timer *timer) |
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{ |
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writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); |
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if (timer->mode & MCHP_PIT64B_MR_SGCLK) |
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clk_disable_unprepare(timer->gclk); |
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clk_disable_unprepare(timer->pclk); |
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} |
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static void mchp_pit64b_resume(struct mchp_pit64b_timer *timer) |
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{ |
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clk_prepare_enable(timer->pclk); |
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if (timer->mode & MCHP_PIT64B_MR_SGCLK) |
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clk_prepare_enable(timer->gclk); |
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} |
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static void mchp_pit64b_clksrc_suspend(struct clocksource *cs) |
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{ |
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struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs); |
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mchp_pit64b_suspend(timer); |
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} |
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static void mchp_pit64b_clksrc_resume(struct clocksource *cs) |
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{ |
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struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs); |
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mchp_pit64b_resume(timer); |
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mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0); |
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} |
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static u64 mchp_pit64b_clksrc_read(struct clocksource *cs) |
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{ |
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return mchp_pit64b_cnt_read(mchp_pit64b_cs_base); |
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} |
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static u64 mchp_pit64b_sched_read_clk(void) |
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{ |
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return mchp_pit64b_cnt_read(mchp_pit64b_cs_base); |
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} |
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static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev) |
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{ |
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struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); |
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writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); |
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return 0; |
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} |
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static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev) |
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{ |
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struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); |
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mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT, |
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MCHP_PIT64B_IER_PERIOD); |
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return 0; |
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} |
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static int mchp_pit64b_clkevt_set_next_event(unsigned long evt, |
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struct clock_event_device *cedev) |
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{ |
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struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); |
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mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT, |
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MCHP_PIT64B_IER_PERIOD); |
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return 0; |
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} |
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static void mchp_pit64b_clkevt_suspend(struct clock_event_device *cedev) |
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{ |
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struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); |
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mchp_pit64b_suspend(timer); |
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} |
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static void mchp_pit64b_clkevt_resume(struct clock_event_device *cedev) |
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{ |
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struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); |
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mchp_pit64b_resume(timer); |
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} |
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static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id) |
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{ |
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struct mchp_pit64b_clkevt *irq_data = dev_id; |
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/* Need to clear the interrupt. */ |
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readl_relaxed(irq_data->timer.base + MCHP_PIT64B_ISR); |
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irq_data->clkevt.event_handler(&irq_data->clkevt); |
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return IRQ_HANDLED; |
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} |
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static void __init mchp_pit64b_pres_compute(u32 *pres, u32 clk_rate, |
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u32 max_rate) |
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{ |
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u32 tmp; |
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for (*pres = 0; *pres < MCHP_PIT64B_PRES_MAX; (*pres)++) { |
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tmp = clk_rate / (*pres + 1); |
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if (tmp <= max_rate) |
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break; |
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} |
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/* Use the bigest prescaler if we didn't match one. */ |
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if (*pres == MCHP_PIT64B_PRES_MAX) |
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*pres = MCHP_PIT64B_PRES_MAX - 1; |
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} |
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/** |
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* mchp_pit64b_init_mode - prepare PIT64B mode register value to be used at |
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* runtime; this includes prescaler and SGCLK bit |
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* |
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* PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to |
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* be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate |
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* could be changed via clock APIs. The chosen clock (pclk or gclk) could be |
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* divided by the internal PIT64B's divider. |
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* |
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* This function, first tries to use GCLK by requesting the desired rate from |
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* PMC and then using the internal PIT64B prescaler, if any, to reach the |
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* requested rate. If PCLK/GCLK < 3 (condition requested by PIT64B hardware) |
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* then the function falls back on using PCLK as clock source for PIT64B timer |
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* choosing the highest prescaler in case it doesn't locate one to match the |
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* requested frequency. |
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* |
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* Below is presented the PIT64B block in relation with PMC: |
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* |
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* PIT64B |
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* PMC +------------------------------------+ |
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* +----+ | +-----+ | |
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* | |-->gclk -->|-->| | +---------+ +-----+ | |
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* | | | | MUX |--->| Divider |->|timer| | |
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* | |-->pclk -->|-->| | +---------+ +-----+ | |
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* +----+ | +-----+ | |
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* | ^ | |
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* | sel | |
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* +------------------------------------+ |
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* |
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* Where: |
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* - gclk rate <= pclk rate/3 |
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* - gclk rate could be requested from PMC |
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* - pclk rate is fixed (cannot be requested from PMC) |
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*/ |
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static int __init mchp_pit64b_init_mode(struct mchp_pit64b_timer *timer, |
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unsigned long max_rate) |
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{ |
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unsigned long pclk_rate, diff = 0, best_diff = ULONG_MAX; |
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long gclk_round = 0; |
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u32 pres, best_pres = 0; |
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pclk_rate = clk_get_rate(timer->pclk); |
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if (!pclk_rate) |
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return -EINVAL; |
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timer->mode = 0; |
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/* Try using GCLK. */ |
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gclk_round = clk_round_rate(timer->gclk, max_rate); |
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if (gclk_round < 0) |
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goto pclk; |
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if (pclk_rate / gclk_round < 3) |
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goto pclk; |
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mchp_pit64b_pres_compute(&pres, gclk_round, max_rate); |
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best_diff = abs(gclk_round / (pres + 1) - max_rate); |
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best_pres = pres; |
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if (!best_diff) { |
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timer->mode |= MCHP_PIT64B_MR_SGCLK; |
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clk_set_rate(timer->gclk, gclk_round); |
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goto done; |
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} |
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pclk: |
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/* Check if requested rate could be obtained using PCLK. */ |
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mchp_pit64b_pres_compute(&pres, pclk_rate, max_rate); |
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diff = abs(pclk_rate / (pres + 1) - max_rate); |
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if (best_diff > diff) { |
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/* Use PCLK. */ |
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best_pres = pres; |
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} else { |
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/* Use GCLK. */ |
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timer->mode |= MCHP_PIT64B_MR_SGCLK; |
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clk_set_rate(timer->gclk, gclk_round); |
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} |
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done: |
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timer->mode |= MCHP_PIT64B_PRES_TO_MODE(best_pres); |
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pr_info("PIT64B: using clk=%s with prescaler %u, freq=%lu [Hz]\n", |
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timer->mode & MCHP_PIT64B_MR_SGCLK ? "gclk" : "pclk", best_pres, |
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timer->mode & MCHP_PIT64B_MR_SGCLK ? |
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gclk_round / (best_pres + 1) : pclk_rate / (best_pres + 1)); |
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return 0; |
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} |
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static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer, |
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u32 clk_rate) |
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{ |
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struct mchp_pit64b_clksrc *cs; |
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int ret; |
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cs = kzalloc(sizeof(*cs), GFP_KERNEL); |
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if (!cs) |
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return -ENOMEM; |
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mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0); |
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mchp_pit64b_cs_base = timer->base; |
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cs->timer.base = timer->base; |
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cs->timer.pclk = timer->pclk; |
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cs->timer.gclk = timer->gclk; |
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cs->timer.mode = timer->mode; |
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cs->clksrc.name = MCHP_PIT64B_NAME; |
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cs->clksrc.mask = CLOCKSOURCE_MASK(64); |
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cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; |
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cs->clksrc.rating = 210; |
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cs->clksrc.read = mchp_pit64b_clksrc_read; |
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cs->clksrc.suspend = mchp_pit64b_clksrc_suspend; |
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cs->clksrc.resume = mchp_pit64b_clksrc_resume; |
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ret = clocksource_register_hz(&cs->clksrc, clk_rate); |
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if (ret) { |
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pr_debug("clksrc: Failed to register PIT64B clocksource!\n"); |
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/* Stop timer. */ |
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writel_relaxed(MCHP_PIT64B_CR_SWRST, |
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timer->base + MCHP_PIT64B_CR); |
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kfree(cs); |
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return ret; |
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} |
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sched_clock_register(mchp_pit64b_sched_read_clk, 64, clk_rate); |
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return 0; |
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} |
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static int __init mchp_pit64b_init_clkevt(struct mchp_pit64b_timer *timer, |
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u32 clk_rate, u32 irq) |
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{ |
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struct mchp_pit64b_clkevt *ce; |
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int ret; |
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ce = kzalloc(sizeof(*ce), GFP_KERNEL); |
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if (!ce) |
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return -ENOMEM; |
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mchp_pit64b_ce_cycles = DIV_ROUND_CLOSEST(clk_rate, HZ); |
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ce->timer.base = timer->base; |
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ce->timer.pclk = timer->pclk; |
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ce->timer.gclk = timer->gclk; |
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ce->timer.mode = timer->mode; |
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ce->clkevt.name = MCHP_PIT64B_NAME; |
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ce->clkevt.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC; |
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ce->clkevt.rating = 150; |
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ce->clkevt.set_state_shutdown = mchp_pit64b_clkevt_shutdown; |
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ce->clkevt.set_state_periodic = mchp_pit64b_clkevt_set_periodic; |
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ce->clkevt.set_next_event = mchp_pit64b_clkevt_set_next_event; |
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ce->clkevt.suspend = mchp_pit64b_clkevt_suspend; |
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ce->clkevt.resume = mchp_pit64b_clkevt_resume; |
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ce->clkevt.cpumask = cpumask_of(0); |
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ce->clkevt.irq = irq; |
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ret = request_irq(irq, mchp_pit64b_interrupt, IRQF_TIMER, |
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"pit64b_tick", ce); |
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if (ret) { |
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pr_debug("clkevt: Failed to setup PIT64B IRQ\n"); |
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kfree(ce); |
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return ret; |
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} |
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clockevents_config_and_register(&ce->clkevt, clk_rate, 1, ULONG_MAX); |
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return 0; |
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} |
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static int __init mchp_pit64b_dt_init_timer(struct device_node *node, |
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bool clkevt) |
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{ |
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u32 freq = clkevt ? MCHP_PIT64B_DEF_CE_FREQ : MCHP_PIT64B_DEF_CS_FREQ; |
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struct mchp_pit64b_timer timer; |
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unsigned long clk_rate; |
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u32 irq = 0; |
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int ret; |
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/* Parse DT node. */ |
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timer.pclk = of_clk_get_by_name(node, "pclk"); |
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if (IS_ERR(timer.pclk)) |
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return PTR_ERR(timer.pclk); |
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timer.gclk = of_clk_get_by_name(node, "gclk"); |
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if (IS_ERR(timer.gclk)) |
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return PTR_ERR(timer.gclk); |
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timer.base = of_iomap(node, 0); |
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if (!timer.base) |
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return -ENXIO; |
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if (clkevt) { |
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irq = irq_of_parse_and_map(node, 0); |
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if (!irq) { |
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ret = -ENODEV; |
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goto io_unmap; |
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} |
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} |
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/* Initialize mode (prescaler + SGCK bit). To be used at runtime. */ |
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ret = mchp_pit64b_init_mode(&timer, freq); |
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if (ret) |
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goto irq_unmap; |
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ret = clk_prepare_enable(timer.pclk); |
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if (ret) |
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goto irq_unmap; |
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if (timer.mode & MCHP_PIT64B_MR_SGCLK) { |
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ret = clk_prepare_enable(timer.gclk); |
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if (ret) |
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goto pclk_unprepare; |
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clk_rate = clk_get_rate(timer.gclk); |
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} else { |
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clk_rate = clk_get_rate(timer.pclk); |
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} |
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clk_rate = clk_rate / (MCHP_PIT64B_MODE_TO_PRES(timer.mode) + 1); |
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if (clkevt) |
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ret = mchp_pit64b_init_clkevt(&timer, clk_rate, irq); |
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else |
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ret = mchp_pit64b_init_clksrc(&timer, clk_rate); |
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if (ret) |
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goto gclk_unprepare; |
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return 0; |
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gclk_unprepare: |
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if (timer.mode & MCHP_PIT64B_MR_SGCLK) |
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clk_disable_unprepare(timer.gclk); |
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pclk_unprepare: |
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clk_disable_unprepare(timer.pclk); |
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irq_unmap: |
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irq_dispose_mapping(irq); |
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io_unmap: |
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iounmap(timer.base); |
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return ret; |
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} |
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static int __init mchp_pit64b_dt_init(struct device_node *node) |
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{ |
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static int inits; |
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|
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switch (inits++) { |
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case 0: |
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/* 1st request, register clockevent. */ |
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return mchp_pit64b_dt_init_timer(node, true); |
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case 1: |
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/* 2nd request, register clocksource. */ |
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return mchp_pit64b_dt_init_timer(node, false); |
|
} |
|
|
|
/* The rest, don't care. */ |
|
return -EINVAL; |
|
} |
|
|
|
TIMER_OF_DECLARE(mchp_pit64b, "microchip,sam9x60-pit64b", mchp_pit64b_dt_init);
|
|
|