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501 lines
12 KiB
501 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2011 Samsung Electronics Co., Ltd. |
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* http://www.samsung.com/ |
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* |
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* samsung - Common hr-timer support (s3c and s5p) |
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*/ |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/err.h> |
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#include <linux/clk.h> |
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#include <linux/clockchips.h> |
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#include <linux/list.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/sched_clock.h> |
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#include <clocksource/samsung_pwm.h> |
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/* |
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* Clocksource driver |
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*/ |
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#define REG_TCFG0 0x00 |
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#define REG_TCFG1 0x04 |
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#define REG_TCON 0x08 |
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#define REG_TINT_CSTAT 0x44 |
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#define REG_TCNTB(chan) (0x0c + 12 * (chan)) |
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#define REG_TCMPB(chan) (0x10 + 12 * (chan)) |
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#define TCFG0_PRESCALER_MASK 0xff |
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#define TCFG0_PRESCALER1_SHIFT 8 |
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#define TCFG1_SHIFT(x) ((x) * 4) |
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#define TCFG1_MUX_MASK 0xf |
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/* |
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* Each channel occupies 4 bits in TCON register, but there is a gap of 4 |
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* bits (one channel) after channel 0, so channels have different numbering |
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* when accessing TCON register. |
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* |
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* In addition, the location of autoreload bit for channel 4 (TCON channel 5) |
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* in its set of bits is 2 as opposed to 3 for other channels. |
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*/ |
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#define TCON_START(chan) (1 << (4 * (chan) + 0)) |
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#define TCON_MANUALUPDATE(chan) (1 << (4 * (chan) + 1)) |
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#define TCON_INVERT(chan) (1 << (4 * (chan) + 2)) |
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#define _TCON_AUTORELOAD(chan) (1 << (4 * (chan) + 3)) |
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#define _TCON_AUTORELOAD4(chan) (1 << (4 * (chan) + 2)) |
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#define TCON_AUTORELOAD(chan) \ |
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((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan)) |
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DEFINE_SPINLOCK(samsung_pwm_lock); |
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EXPORT_SYMBOL(samsung_pwm_lock); |
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struct samsung_pwm_clocksource { |
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void __iomem *base; |
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void __iomem *source_reg; |
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unsigned int irq[SAMSUNG_PWM_NUM]; |
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struct samsung_pwm_variant variant; |
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struct clk *timerclk; |
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unsigned int event_id; |
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unsigned int source_id; |
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unsigned int tcnt_max; |
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unsigned int tscaler_div; |
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unsigned int tdiv; |
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unsigned long clock_count_per_tick; |
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}; |
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static struct samsung_pwm_clocksource pwm; |
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static void samsung_timer_set_prescale(unsigned int channel, u16 prescale) |
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{ |
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unsigned long flags; |
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u8 shift = 0; |
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u32 reg; |
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if (channel >= 2) |
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shift = TCFG0_PRESCALER1_SHIFT; |
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spin_lock_irqsave(&samsung_pwm_lock, flags); |
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reg = readl(pwm.base + REG_TCFG0); |
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reg &= ~(TCFG0_PRESCALER_MASK << shift); |
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reg |= (prescale - 1) << shift; |
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writel(reg, pwm.base + REG_TCFG0); |
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spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
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} |
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static void samsung_timer_set_divisor(unsigned int channel, u8 divisor) |
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{ |
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u8 shift = TCFG1_SHIFT(channel); |
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unsigned long flags; |
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u32 reg; |
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u8 bits; |
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bits = (fls(divisor) - 1) - pwm.variant.div_base; |
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spin_lock_irqsave(&samsung_pwm_lock, flags); |
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reg = readl(pwm.base + REG_TCFG1); |
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reg &= ~(TCFG1_MUX_MASK << shift); |
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reg |= bits << shift; |
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writel(reg, pwm.base + REG_TCFG1); |
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spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
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} |
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static void samsung_time_stop(unsigned int channel) |
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{ |
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unsigned long tcon; |
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unsigned long flags; |
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if (channel > 0) |
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++channel; |
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spin_lock_irqsave(&samsung_pwm_lock, flags); |
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tcon = readl_relaxed(pwm.base + REG_TCON); |
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tcon &= ~TCON_START(channel); |
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writel_relaxed(tcon, pwm.base + REG_TCON); |
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spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
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} |
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static void samsung_time_setup(unsigned int channel, unsigned long tcnt) |
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{ |
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unsigned long tcon; |
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unsigned long flags; |
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unsigned int tcon_chan = channel; |
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if (tcon_chan > 0) |
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++tcon_chan; |
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spin_lock_irqsave(&samsung_pwm_lock, flags); |
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tcon = readl_relaxed(pwm.base + REG_TCON); |
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tcon &= ~(TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan)); |
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tcon |= TCON_MANUALUPDATE(tcon_chan); |
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writel_relaxed(tcnt, pwm.base + REG_TCNTB(channel)); |
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writel_relaxed(tcnt, pwm.base + REG_TCMPB(channel)); |
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writel_relaxed(tcon, pwm.base + REG_TCON); |
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spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
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} |
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static void samsung_time_start(unsigned int channel, bool periodic) |
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{ |
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unsigned long tcon; |
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unsigned long flags; |
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if (channel > 0) |
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++channel; |
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spin_lock_irqsave(&samsung_pwm_lock, flags); |
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tcon = readl_relaxed(pwm.base + REG_TCON); |
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tcon &= ~TCON_MANUALUPDATE(channel); |
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tcon |= TCON_START(channel); |
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if (periodic) |
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tcon |= TCON_AUTORELOAD(channel); |
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else |
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tcon &= ~TCON_AUTORELOAD(channel); |
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writel_relaxed(tcon, pwm.base + REG_TCON); |
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spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
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} |
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static int samsung_set_next_event(unsigned long cycles, |
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struct clock_event_device *evt) |
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{ |
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/* |
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* This check is needed to account for internal rounding |
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* errors inside clockevents core, which might result in |
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* passing cycles = 0, which in turn would not generate any |
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* timer interrupt and hang the system. |
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* |
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* Another solution would be to set up the clockevent device |
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* with min_delta = 2, but this would unnecessarily increase |
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* the minimum sleep period. |
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*/ |
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if (!cycles) |
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cycles = 1; |
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samsung_time_setup(pwm.event_id, cycles); |
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samsung_time_start(pwm.event_id, false); |
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return 0; |
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} |
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static int samsung_shutdown(struct clock_event_device *evt) |
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{ |
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samsung_time_stop(pwm.event_id); |
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return 0; |
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} |
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static int samsung_set_periodic(struct clock_event_device *evt) |
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{ |
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samsung_time_stop(pwm.event_id); |
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samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1); |
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samsung_time_start(pwm.event_id, true); |
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return 0; |
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} |
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static void samsung_clockevent_resume(struct clock_event_device *cev) |
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{ |
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samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div); |
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samsung_timer_set_divisor(pwm.event_id, pwm.tdiv); |
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if (pwm.variant.has_tint_cstat) { |
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u32 mask = (1 << pwm.event_id); |
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writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT); |
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} |
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} |
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static struct clock_event_device time_event_device = { |
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.name = "samsung_event_timer", |
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.features = CLOCK_EVT_FEAT_PERIODIC | |
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CLOCK_EVT_FEAT_ONESHOT, |
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.rating = 200, |
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.set_next_event = samsung_set_next_event, |
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.set_state_shutdown = samsung_shutdown, |
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.set_state_periodic = samsung_set_periodic, |
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.set_state_oneshot = samsung_shutdown, |
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.tick_resume = samsung_shutdown, |
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.resume = samsung_clockevent_resume, |
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}; |
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static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id) |
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{ |
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struct clock_event_device *evt = dev_id; |
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if (pwm.variant.has_tint_cstat) { |
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u32 mask = (1 << pwm.event_id); |
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writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT); |
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} |
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evt->event_handler(evt); |
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return IRQ_HANDLED; |
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} |
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static void __init samsung_clockevent_init(void) |
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{ |
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unsigned long pclk; |
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unsigned long clock_rate; |
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unsigned int irq_number; |
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pclk = clk_get_rate(pwm.timerclk); |
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samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div); |
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samsung_timer_set_divisor(pwm.event_id, pwm.tdiv); |
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clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv); |
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pwm.clock_count_per_tick = clock_rate / HZ; |
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time_event_device.cpumask = cpumask_of(0); |
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clockevents_config_and_register(&time_event_device, |
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clock_rate, 1, pwm.tcnt_max); |
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irq_number = pwm.irq[pwm.event_id]; |
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if (request_irq(irq_number, samsung_clock_event_isr, |
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IRQF_TIMER | IRQF_IRQPOLL, "samsung_time_irq", |
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&time_event_device)) |
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pr_err("%s: request_irq() failed\n", "samsung_time_irq"); |
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if (pwm.variant.has_tint_cstat) { |
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u32 mask = (1 << pwm.event_id); |
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writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT); |
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} |
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} |
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static void samsung_clocksource_suspend(struct clocksource *cs) |
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{ |
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samsung_time_stop(pwm.source_id); |
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} |
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static void samsung_clocksource_resume(struct clocksource *cs) |
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{ |
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samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div); |
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samsung_timer_set_divisor(pwm.source_id, pwm.tdiv); |
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samsung_time_setup(pwm.source_id, pwm.tcnt_max); |
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samsung_time_start(pwm.source_id, true); |
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} |
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static u64 notrace samsung_clocksource_read(struct clocksource *c) |
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{ |
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return ~readl_relaxed(pwm.source_reg); |
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} |
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static struct clocksource samsung_clocksource = { |
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.name = "samsung_clocksource_timer", |
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.rating = 250, |
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.read = samsung_clocksource_read, |
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.suspend = samsung_clocksource_suspend, |
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.resume = samsung_clocksource_resume, |
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.flags = CLOCK_SOURCE_IS_CONTINUOUS, |
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}; |
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/* |
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* Override the global weak sched_clock symbol with this |
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* local implementation which uses the clocksource to get some |
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* better resolution when scheduling the kernel. We accept that |
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* this wraps around for now, since it is just a relative time |
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* stamp. (Inspired by U300 implementation.) |
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*/ |
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static u64 notrace samsung_read_sched_clock(void) |
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{ |
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return samsung_clocksource_read(NULL); |
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} |
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static int __init samsung_clocksource_init(void) |
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{ |
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unsigned long pclk; |
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unsigned long clock_rate; |
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pclk = clk_get_rate(pwm.timerclk); |
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samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div); |
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samsung_timer_set_divisor(pwm.source_id, pwm.tdiv); |
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clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv); |
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samsung_time_setup(pwm.source_id, pwm.tcnt_max); |
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samsung_time_start(pwm.source_id, true); |
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if (pwm.source_id == 4) |
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pwm.source_reg = pwm.base + 0x40; |
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else |
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pwm.source_reg = pwm.base + pwm.source_id * 0x0c + 0x14; |
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sched_clock_register(samsung_read_sched_clock, |
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pwm.variant.bits, clock_rate); |
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samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits); |
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return clocksource_register_hz(&samsung_clocksource, clock_rate); |
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} |
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static void __init samsung_timer_resources(void) |
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{ |
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clk_prepare_enable(pwm.timerclk); |
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pwm.tcnt_max = (1UL << pwm.variant.bits) - 1; |
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if (pwm.variant.bits == 16) { |
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pwm.tscaler_div = 25; |
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pwm.tdiv = 2; |
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} else { |
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pwm.tscaler_div = 2; |
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pwm.tdiv = 1; |
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} |
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} |
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/* |
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* PWM master driver |
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*/ |
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static int __init _samsung_pwm_clocksource_init(void) |
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{ |
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u8 mask; |
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int channel; |
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mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1); |
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channel = fls(mask) - 1; |
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if (channel < 0) { |
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pr_crit("failed to find PWM channel for clocksource\n"); |
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return -EINVAL; |
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} |
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pwm.source_id = channel; |
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mask &= ~(1 << channel); |
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channel = fls(mask) - 1; |
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if (channel < 0) { |
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pr_crit("failed to find PWM channel for clock event\n"); |
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return -EINVAL; |
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} |
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pwm.event_id = channel; |
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samsung_timer_resources(); |
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samsung_clockevent_init(); |
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return samsung_clocksource_init(); |
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} |
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void __init samsung_pwm_clocksource_init(void __iomem *base, |
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unsigned int *irqs, struct samsung_pwm_variant *variant) |
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{ |
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pwm.base = base; |
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memcpy(&pwm.variant, variant, sizeof(pwm.variant)); |
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memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs)); |
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pwm.timerclk = clk_get(NULL, "timers"); |
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if (IS_ERR(pwm.timerclk)) |
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panic("failed to get timers clock for timer"); |
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_samsung_pwm_clocksource_init(); |
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} |
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#ifdef CONFIG_TIMER_OF |
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static int __init samsung_pwm_alloc(struct device_node *np, |
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const struct samsung_pwm_variant *variant) |
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{ |
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struct property *prop; |
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const __be32 *cur; |
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u32 val; |
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int i; |
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memcpy(&pwm.variant, variant, sizeof(pwm.variant)); |
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for (i = 0; i < SAMSUNG_PWM_NUM; ++i) |
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pwm.irq[i] = irq_of_parse_and_map(np, i); |
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of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) { |
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if (val >= SAMSUNG_PWM_NUM) { |
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pr_warn("%s: invalid channel index in samsung,pwm-outputs property\n", __func__); |
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continue; |
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} |
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pwm.variant.output_mask |= 1 << val; |
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} |
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pwm.base = of_iomap(np, 0); |
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if (!pwm.base) { |
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pr_err("%s: failed to map PWM registers\n", __func__); |
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return -ENXIO; |
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} |
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pwm.timerclk = of_clk_get_by_name(np, "timers"); |
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if (IS_ERR(pwm.timerclk)) { |
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pr_crit("failed to get timers clock for timer\n"); |
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return PTR_ERR(pwm.timerclk); |
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} |
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return _samsung_pwm_clocksource_init(); |
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} |
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static const struct samsung_pwm_variant s3c24xx_variant = { |
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.bits = 16, |
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.div_base = 1, |
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.has_tint_cstat = false, |
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.tclk_mask = (1 << 4), |
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}; |
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static int __init s3c2410_pwm_clocksource_init(struct device_node *np) |
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{ |
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return samsung_pwm_alloc(np, &s3c24xx_variant); |
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} |
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TIMER_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init); |
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static const struct samsung_pwm_variant s3c64xx_variant = { |
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.bits = 32, |
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.div_base = 0, |
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.has_tint_cstat = true, |
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.tclk_mask = (1 << 7) | (1 << 6) | (1 << 5), |
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}; |
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static int __init s3c64xx_pwm_clocksource_init(struct device_node *np) |
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{ |
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return samsung_pwm_alloc(np, &s3c64xx_variant); |
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} |
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TIMER_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init); |
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static const struct samsung_pwm_variant s5p64x0_variant = { |
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.bits = 32, |
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.div_base = 0, |
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.has_tint_cstat = true, |
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.tclk_mask = 0, |
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}; |
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static int __init s5p64x0_pwm_clocksource_init(struct device_node *np) |
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{ |
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return samsung_pwm_alloc(np, &s5p64x0_variant); |
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} |
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TIMER_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init); |
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static const struct samsung_pwm_variant s5p_variant = { |
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.bits = 32, |
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.div_base = 0, |
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.has_tint_cstat = true, |
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.tclk_mask = (1 << 5), |
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}; |
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static int __init s5p_pwm_clocksource_init(struct device_node *np) |
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{ |
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return samsung_pwm_alloc(np, &s5p_variant); |
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} |
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TIMER_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init); |
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#endif
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