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211 lines
4.8 KiB
211 lines
4.8 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Renesas Timer Support - OSTM |
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* |
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* Copyright (C) 2017 Renesas Electronics America, Inc. |
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* Copyright (C) 2017 Chris Brandt |
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*/ |
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#include <linux/clk.h> |
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#include <linux/clockchips.h> |
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#include <linux/interrupt.h> |
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#include <linux/sched_clock.h> |
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#include <linux/slab.h> |
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#include "timer-of.h" |
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/* |
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* The OSTM contains independent channels. |
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* The first OSTM channel probed will be set up as a free running |
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* clocksource. Additionally we will use this clocksource for the system |
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* schedule timer sched_clock(). |
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* |
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* The second (or more) channel probed will be set up as an interrupt |
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* driven clock event. |
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*/ |
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static void __iomem *system_clock; /* For sched_clock() */ |
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/* OSTM REGISTERS */ |
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#define OSTM_CMP 0x000 /* RW,32 */ |
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#define OSTM_CNT 0x004 /* R,32 */ |
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#define OSTM_TE 0x010 /* R,8 */ |
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#define OSTM_TS 0x014 /* W,8 */ |
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#define OSTM_TT 0x018 /* W,8 */ |
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#define OSTM_CTL 0x020 /* RW,8 */ |
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#define TE 0x01 |
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#define TS 0x01 |
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#define TT 0x01 |
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#define CTL_PERIODIC 0x00 |
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#define CTL_ONESHOT 0x02 |
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#define CTL_FREERUN 0x02 |
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static void ostm_timer_stop(struct timer_of *to) |
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{ |
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if (readb(timer_of_base(to) + OSTM_TE) & TE) { |
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writeb(TT, timer_of_base(to) + OSTM_TT); |
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/* |
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* Read back the register simply to confirm the write operation |
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* has completed since I/O writes can sometimes get queued by |
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* the bus architecture. |
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*/ |
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while (readb(timer_of_base(to) + OSTM_TE) & TE) |
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; |
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} |
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} |
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static int __init ostm_init_clksrc(struct timer_of *to) |
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{ |
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ostm_timer_stop(to); |
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writel(0, timer_of_base(to) + OSTM_CMP); |
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writeb(CTL_FREERUN, timer_of_base(to) + OSTM_CTL); |
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writeb(TS, timer_of_base(to) + OSTM_TS); |
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return clocksource_mmio_init(timer_of_base(to) + OSTM_CNT, |
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to->np->full_name, timer_of_rate(to), 300, |
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32, clocksource_mmio_readl_up); |
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} |
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static u64 notrace ostm_read_sched_clock(void) |
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{ |
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return readl(system_clock); |
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} |
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static void __init ostm_init_sched_clock(struct timer_of *to) |
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{ |
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system_clock = timer_of_base(to) + OSTM_CNT; |
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sched_clock_register(ostm_read_sched_clock, 32, timer_of_rate(to)); |
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} |
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static int ostm_clock_event_next(unsigned long delta, |
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struct clock_event_device *ced) |
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{ |
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struct timer_of *to = to_timer_of(ced); |
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ostm_timer_stop(to); |
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writel(delta, timer_of_base(to) + OSTM_CMP); |
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writeb(CTL_ONESHOT, timer_of_base(to) + OSTM_CTL); |
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writeb(TS, timer_of_base(to) + OSTM_TS); |
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return 0; |
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} |
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static int ostm_shutdown(struct clock_event_device *ced) |
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{ |
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struct timer_of *to = to_timer_of(ced); |
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ostm_timer_stop(to); |
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return 0; |
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} |
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static int ostm_set_periodic(struct clock_event_device *ced) |
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{ |
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struct timer_of *to = to_timer_of(ced); |
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if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) |
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ostm_timer_stop(to); |
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writel(timer_of_period(to) - 1, timer_of_base(to) + OSTM_CMP); |
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writeb(CTL_PERIODIC, timer_of_base(to) + OSTM_CTL); |
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writeb(TS, timer_of_base(to) + OSTM_TS); |
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return 0; |
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} |
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static int ostm_set_oneshot(struct clock_event_device *ced) |
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{ |
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struct timer_of *to = to_timer_of(ced); |
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ostm_timer_stop(to); |
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return 0; |
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} |
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static irqreturn_t ostm_timer_interrupt(int irq, void *dev_id) |
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{ |
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struct clock_event_device *ced = dev_id; |
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if (clockevent_state_oneshot(ced)) |
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ostm_timer_stop(to_timer_of(ced)); |
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/* notify clockevent layer */ |
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if (ced->event_handler) |
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ced->event_handler(ced); |
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return IRQ_HANDLED; |
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} |
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static int __init ostm_init_clkevt(struct timer_of *to) |
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{ |
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struct clock_event_device *ced = &to->clkevt; |
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ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC; |
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ced->set_state_shutdown = ostm_shutdown; |
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ced->set_state_periodic = ostm_set_periodic; |
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ced->set_state_oneshot = ostm_set_oneshot; |
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ced->set_next_event = ostm_clock_event_next; |
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ced->shift = 32; |
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ced->rating = 300; |
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ced->cpumask = cpumask_of(0); |
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clockevents_config_and_register(ced, timer_of_rate(to), 0xf, |
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0xffffffff); |
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return 0; |
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} |
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static int __init ostm_init(struct device_node *np) |
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{ |
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struct timer_of *to; |
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int ret; |
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to = kzalloc(sizeof(*to), GFP_KERNEL); |
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if (!to) |
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return -ENOMEM; |
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to->flags = TIMER_OF_BASE | TIMER_OF_CLOCK; |
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if (system_clock) { |
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/* |
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* clock sources don't use interrupts, clock events do |
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*/ |
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to->flags |= TIMER_OF_IRQ; |
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to->of_irq.flags = IRQF_TIMER | IRQF_IRQPOLL; |
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to->of_irq.handler = ostm_timer_interrupt; |
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} |
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ret = timer_of_init(np, to); |
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if (ret) |
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goto err_free; |
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/* |
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* First probed device will be used as system clocksource. Any |
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* additional devices will be used as clock events. |
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*/ |
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if (!system_clock) { |
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ret = ostm_init_clksrc(to); |
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if (ret) |
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goto err_cleanup; |
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ostm_init_sched_clock(to); |
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pr_info("%pOF: used for clocksource\n", np); |
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} else { |
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ret = ostm_init_clkevt(to); |
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if (ret) |
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goto err_cleanup; |
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pr_info("%pOF: used for clock events\n", np); |
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} |
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return 0; |
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err_cleanup: |
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timer_of_cleanup(to); |
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err_free: |
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kfree(to); |
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return ret; |
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} |
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TIMER_OF_DECLARE(ostm, "renesas,ostm", ostm_init);
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