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743 lines
19 KiB
743 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Xilinx VCU Init |
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* |
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* Copyright (C) 2016 - 2017 Xilinx, Inc. |
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* |
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* Contacts Dhaval Shah <[email protected]> |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/device.h> |
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#include <linux/errno.h> |
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#include <linux/io.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/mfd/syscon/xlnx-vcu.h> |
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#include <linux/module.h> |
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#include <linux/of_platform.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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|
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#include <dt-bindings/clock/xlnx-vcu.h> |
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|
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#define VCU_PLL_CTRL 0x24 |
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#define VCU_PLL_CTRL_RESET BIT(0) |
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#define VCU_PLL_CTRL_POR_IN BIT(1) |
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#define VCU_PLL_CTRL_PWR_POR BIT(2) |
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#define VCU_PLL_CTRL_BYPASS BIT(3) |
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#define VCU_PLL_CTRL_FBDIV GENMASK(14, 8) |
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#define VCU_PLL_CTRL_CLKOUTDIV GENMASK(18, 16) |
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|
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#define VCU_PLL_CFG 0x28 |
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#define VCU_PLL_CFG_RES GENMASK(3, 0) |
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#define VCU_PLL_CFG_CP GENMASK(8, 5) |
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#define VCU_PLL_CFG_LFHF GENMASK(12, 10) |
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#define VCU_PLL_CFG_LOCK_CNT GENMASK(22, 13) |
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#define VCU_PLL_CFG_LOCK_DLY GENMASK(31, 25) |
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#define VCU_ENC_CORE_CTRL 0x30 |
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#define VCU_ENC_MCU_CTRL 0x34 |
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#define VCU_DEC_CORE_CTRL 0x38 |
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#define VCU_DEC_MCU_CTRL 0x3c |
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#define VCU_PLL_STATUS 0x60 |
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#define VCU_PLL_STATUS_LOCK_STATUS BIT(0) |
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|
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#define MHZ 1000000 |
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#define FVCO_MIN (1500U * MHZ) |
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#define FVCO_MAX (3000U * MHZ) |
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|
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/** |
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* struct xvcu_device - Xilinx VCU init device structure |
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* @dev: Platform device |
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* @pll_ref: pll ref clock source |
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* @aclk: axi clock source |
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* @logicore_reg_ba: logicore reg base address |
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* @vcu_slcr_ba: vcu_slcr Register base address |
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* @pll: handle for the VCU PLL |
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* @pll_post: handle for the VCU PLL post divider |
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* @clk_data: clocks provided by the vcu clock provider |
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*/ |
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struct xvcu_device { |
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struct device *dev; |
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struct clk *pll_ref; |
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struct clk *aclk; |
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struct regmap *logicore_reg_ba; |
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void __iomem *vcu_slcr_ba; |
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struct clk_hw *pll; |
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struct clk_hw *pll_post; |
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struct clk_hw_onecell_data *clk_data; |
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}; |
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|
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static struct regmap_config vcu_settings_regmap_config = { |
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.name = "regmap", |
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.reg_bits = 32, |
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.val_bits = 32, |
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.reg_stride = 4, |
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.max_register = 0xfff, |
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.cache_type = REGCACHE_NONE, |
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}; |
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|
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/** |
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* struct xvcu_pll_cfg - Helper data |
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* @fbdiv: The integer portion of the feedback divider to the PLL |
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* @cp: PLL charge pump control |
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* @res: PLL loop filter resistor control |
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* @lfhf: PLL loop filter high frequency capacitor control |
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* @lock_dly: Lock circuit configuration settings for lock windowsize |
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* @lock_cnt: Lock circuit counter setting |
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*/ |
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struct xvcu_pll_cfg { |
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u32 fbdiv; |
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u32 cp; |
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u32 res; |
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u32 lfhf; |
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u32 lock_dly; |
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u32 lock_cnt; |
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}; |
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|
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static const struct xvcu_pll_cfg xvcu_pll_cfg[] = { |
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{ 25, 3, 10, 3, 63, 1000 }, |
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{ 26, 3, 10, 3, 63, 1000 }, |
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{ 27, 4, 6, 3, 63, 1000 }, |
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{ 28, 4, 6, 3, 63, 1000 }, |
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{ 29, 4, 6, 3, 63, 1000 }, |
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{ 30, 4, 6, 3, 63, 1000 }, |
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{ 31, 6, 1, 3, 63, 1000 }, |
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{ 32, 6, 1, 3, 63, 1000 }, |
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{ 33, 4, 10, 3, 63, 1000 }, |
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{ 34, 5, 6, 3, 63, 1000 }, |
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{ 35, 5, 6, 3, 63, 1000 }, |
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{ 36, 5, 6, 3, 63, 1000 }, |
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{ 37, 5, 6, 3, 63, 1000 }, |
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{ 38, 5, 6, 3, 63, 975 }, |
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{ 39, 3, 12, 3, 63, 950 }, |
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{ 40, 3, 12, 3, 63, 925 }, |
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{ 41, 3, 12, 3, 63, 900 }, |
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{ 42, 3, 12, 3, 63, 875 }, |
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{ 43, 3, 12, 3, 63, 850 }, |
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{ 44, 3, 12, 3, 63, 850 }, |
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{ 45, 3, 12, 3, 63, 825 }, |
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{ 46, 3, 12, 3, 63, 800 }, |
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{ 47, 3, 12, 3, 63, 775 }, |
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{ 48, 3, 12, 3, 63, 775 }, |
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{ 49, 3, 12, 3, 63, 750 }, |
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{ 50, 3, 12, 3, 63, 750 }, |
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{ 51, 3, 2, 3, 63, 725 }, |
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{ 52, 3, 2, 3, 63, 700 }, |
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{ 53, 3, 2, 3, 63, 700 }, |
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{ 54, 3, 2, 3, 63, 675 }, |
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{ 55, 3, 2, 3, 63, 675 }, |
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{ 56, 3, 2, 3, 63, 650 }, |
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{ 57, 3, 2, 3, 63, 650 }, |
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{ 58, 3, 2, 3, 63, 625 }, |
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{ 59, 3, 2, 3, 63, 625 }, |
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{ 60, 3, 2, 3, 63, 625 }, |
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{ 61, 3, 2, 3, 63, 600 }, |
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{ 62, 3, 2, 3, 63, 600 }, |
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{ 63, 3, 2, 3, 63, 600 }, |
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{ 64, 3, 2, 3, 63, 600 }, |
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{ 65, 3, 2, 3, 63, 600 }, |
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{ 66, 3, 2, 3, 63, 600 }, |
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{ 67, 3, 2, 3, 63, 600 }, |
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{ 68, 3, 2, 3, 63, 600 }, |
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{ 69, 3, 2, 3, 63, 600 }, |
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{ 70, 3, 2, 3, 63, 600 }, |
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{ 71, 3, 2, 3, 63, 600 }, |
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{ 72, 3, 2, 3, 63, 600 }, |
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{ 73, 3, 2, 3, 63, 600 }, |
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{ 74, 3, 2, 3, 63, 600 }, |
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{ 75, 3, 2, 3, 63, 600 }, |
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{ 76, 3, 2, 3, 63, 600 }, |
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{ 77, 3, 2, 3, 63, 600 }, |
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{ 78, 3, 2, 3, 63, 600 }, |
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{ 79, 3, 2, 3, 63, 600 }, |
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{ 80, 3, 2, 3, 63, 600 }, |
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{ 81, 3, 2, 3, 63, 600 }, |
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{ 82, 3, 2, 3, 63, 600 }, |
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{ 83, 4, 2, 3, 63, 600 }, |
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{ 84, 4, 2, 3, 63, 600 }, |
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{ 85, 4, 2, 3, 63, 600 }, |
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{ 86, 4, 2, 3, 63, 600 }, |
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{ 87, 4, 2, 3, 63, 600 }, |
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{ 88, 4, 2, 3, 63, 600 }, |
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{ 89, 4, 2, 3, 63, 600 }, |
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{ 90, 4, 2, 3, 63, 600 }, |
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{ 91, 4, 2, 3, 63, 600 }, |
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{ 92, 4, 2, 3, 63, 600 }, |
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{ 93, 4, 2, 3, 63, 600 }, |
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{ 94, 4, 2, 3, 63, 600 }, |
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{ 95, 4, 2, 3, 63, 600 }, |
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{ 96, 4, 2, 3, 63, 600 }, |
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{ 97, 4, 2, 3, 63, 600 }, |
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{ 98, 4, 2, 3, 63, 600 }, |
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{ 99, 4, 2, 3, 63, 600 }, |
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{ 100, 4, 2, 3, 63, 600 }, |
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{ 101, 4, 2, 3, 63, 600 }, |
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{ 102, 4, 2, 3, 63, 600 }, |
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{ 103, 5, 2, 3, 63, 600 }, |
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{ 104, 5, 2, 3, 63, 600 }, |
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{ 105, 5, 2, 3, 63, 600 }, |
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{ 106, 5, 2, 3, 63, 600 }, |
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{ 107, 3, 4, 3, 63, 600 }, |
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{ 108, 3, 4, 3, 63, 600 }, |
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{ 109, 3, 4, 3, 63, 600 }, |
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{ 110, 3, 4, 3, 63, 600 }, |
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{ 111, 3, 4, 3, 63, 600 }, |
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{ 112, 3, 4, 3, 63, 600 }, |
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{ 113, 3, 4, 3, 63, 600 }, |
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{ 114, 3, 4, 3, 63, 600 }, |
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{ 115, 3, 4, 3, 63, 600 }, |
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{ 116, 3, 4, 3, 63, 600 }, |
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{ 117, 3, 4, 3, 63, 600 }, |
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{ 118, 3, 4, 3, 63, 600 }, |
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{ 119, 3, 4, 3, 63, 600 }, |
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{ 120, 3, 4, 3, 63, 600 }, |
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{ 121, 3, 4, 3, 63, 600 }, |
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{ 122, 3, 4, 3, 63, 600 }, |
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{ 123, 3, 4, 3, 63, 600 }, |
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{ 124, 3, 4, 3, 63, 600 }, |
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{ 125, 3, 4, 3, 63, 600 }, |
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}; |
|
|
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/** |
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* xvcu_read - Read from the VCU register space |
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* @iomem: vcu reg space base address |
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* @offset: vcu reg offset from base |
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* |
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* Return: Returns 32bit value from VCU register specified |
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* |
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*/ |
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static inline u32 xvcu_read(void __iomem *iomem, u32 offset) |
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{ |
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return ioread32(iomem + offset); |
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} |
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|
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/** |
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* xvcu_write - Write to the VCU register space |
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* @iomem: vcu reg space base address |
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* @offset: vcu reg offset from base |
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* @value: Value to write |
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*/ |
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static inline void xvcu_write(void __iomem *iomem, u32 offset, u32 value) |
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{ |
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iowrite32(value, iomem + offset); |
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} |
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|
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#define to_vcu_pll(_hw) container_of(_hw, struct vcu_pll, hw) |
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|
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struct vcu_pll { |
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struct clk_hw hw; |
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void __iomem *reg_base; |
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unsigned long fvco_min; |
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unsigned long fvco_max; |
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}; |
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|
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static int xvcu_pll_wait_for_lock(struct vcu_pll *pll) |
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{ |
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void __iomem *base = pll->reg_base; |
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unsigned long timeout; |
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u32 lock_status; |
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|
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timeout = jiffies + msecs_to_jiffies(2000); |
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do { |
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lock_status = xvcu_read(base, VCU_PLL_STATUS); |
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if (lock_status & VCU_PLL_STATUS_LOCK_STATUS) |
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return 0; |
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} while (!time_after(jiffies, timeout)); |
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|
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return -ETIMEDOUT; |
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} |
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|
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static struct clk_hw *xvcu_register_pll_post(struct device *dev, |
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const char *name, |
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const struct clk_hw *parent_hw, |
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void __iomem *reg_base) |
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{ |
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u32 div; |
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u32 vcu_pll_ctrl; |
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|
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/* |
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* The output divider of the PLL must be set to 1/2 to meet the |
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* timing in the design. |
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*/ |
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vcu_pll_ctrl = xvcu_read(reg_base, VCU_PLL_CTRL); |
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div = FIELD_GET(VCU_PLL_CTRL_CLKOUTDIV, vcu_pll_ctrl); |
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if (div != 1) |
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return ERR_PTR(-EINVAL); |
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|
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return clk_hw_register_fixed_factor(dev, "vcu_pll_post", |
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clk_hw_get_name(parent_hw), |
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CLK_SET_RATE_PARENT, 1, 2); |
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} |
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|
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static const struct xvcu_pll_cfg *xvcu_find_cfg(int div) |
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{ |
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const struct xvcu_pll_cfg *cfg = NULL; |
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unsigned int i; |
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|
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for (i = 0; i < ARRAY_SIZE(xvcu_pll_cfg) - 1; i++) |
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if (xvcu_pll_cfg[i].fbdiv == div) |
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cfg = &xvcu_pll_cfg[i]; |
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|
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return cfg; |
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} |
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|
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static int xvcu_pll_set_div(struct vcu_pll *pll, int div) |
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{ |
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void __iomem *base = pll->reg_base; |
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const struct xvcu_pll_cfg *cfg = NULL; |
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u32 vcu_pll_ctrl; |
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u32 cfg_val; |
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cfg = xvcu_find_cfg(div); |
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if (!cfg) |
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return -EINVAL; |
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vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL); |
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vcu_pll_ctrl &= ~VCU_PLL_CTRL_FBDIV; |
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vcu_pll_ctrl |= FIELD_PREP(VCU_PLL_CTRL_FBDIV, cfg->fbdiv); |
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xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl); |
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|
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cfg_val = FIELD_PREP(VCU_PLL_CFG_RES, cfg->res) | |
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FIELD_PREP(VCU_PLL_CFG_CP, cfg->cp) | |
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FIELD_PREP(VCU_PLL_CFG_LFHF, cfg->lfhf) | |
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FIELD_PREP(VCU_PLL_CFG_LOCK_CNT, cfg->lock_cnt) | |
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FIELD_PREP(VCU_PLL_CFG_LOCK_DLY, cfg->lock_dly); |
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xvcu_write(base, VCU_PLL_CFG, cfg_val); |
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|
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return 0; |
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} |
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|
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static long xvcu_pll_round_rate(struct clk_hw *hw, |
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unsigned long rate, unsigned long *parent_rate) |
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{ |
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struct vcu_pll *pll = to_vcu_pll(hw); |
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unsigned int feedback_div; |
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|
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rate = clamp_t(unsigned long, rate, pll->fvco_min, pll->fvco_max); |
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|
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feedback_div = DIV_ROUND_CLOSEST_ULL(rate, *parent_rate); |
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feedback_div = clamp_t(unsigned int, feedback_div, 25, 125); |
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|
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return *parent_rate * feedback_div; |
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} |
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|
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static unsigned long xvcu_pll_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct vcu_pll *pll = to_vcu_pll(hw); |
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void __iomem *base = pll->reg_base; |
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unsigned int div; |
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u32 vcu_pll_ctrl; |
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|
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vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL); |
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div = FIELD_GET(VCU_PLL_CTRL_FBDIV, vcu_pll_ctrl); |
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|
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return div * parent_rate; |
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} |
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|
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static int xvcu_pll_set_rate(struct clk_hw *hw, |
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unsigned long rate, unsigned long parent_rate) |
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{ |
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struct vcu_pll *pll = to_vcu_pll(hw); |
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|
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return xvcu_pll_set_div(pll, rate / parent_rate); |
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} |
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|
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static int xvcu_pll_enable(struct clk_hw *hw) |
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{ |
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struct vcu_pll *pll = to_vcu_pll(hw); |
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void __iomem *base = pll->reg_base; |
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u32 vcu_pll_ctrl; |
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int ret; |
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|
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vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL); |
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vcu_pll_ctrl |= VCU_PLL_CTRL_BYPASS; |
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xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl); |
|
|
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vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL); |
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vcu_pll_ctrl &= ~VCU_PLL_CTRL_POR_IN; |
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vcu_pll_ctrl &= ~VCU_PLL_CTRL_PWR_POR; |
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vcu_pll_ctrl &= ~VCU_PLL_CTRL_RESET; |
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xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl); |
|
|
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ret = xvcu_pll_wait_for_lock(pll); |
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if (ret) { |
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pr_err("VCU PLL is not locked\n"); |
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goto err; |
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} |
|
|
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vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL); |
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vcu_pll_ctrl &= ~VCU_PLL_CTRL_BYPASS; |
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xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl); |
|
|
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err: |
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return ret; |
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} |
|
|
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static void xvcu_pll_disable(struct clk_hw *hw) |
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{ |
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struct vcu_pll *pll = to_vcu_pll(hw); |
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void __iomem *base = pll->reg_base; |
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u32 vcu_pll_ctrl; |
|
|
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vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL); |
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vcu_pll_ctrl |= VCU_PLL_CTRL_POR_IN; |
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vcu_pll_ctrl |= VCU_PLL_CTRL_PWR_POR; |
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vcu_pll_ctrl |= VCU_PLL_CTRL_RESET; |
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xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl); |
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} |
|
|
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static const struct clk_ops vcu_pll_ops = { |
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.enable = xvcu_pll_enable, |
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.disable = xvcu_pll_disable, |
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.round_rate = xvcu_pll_round_rate, |
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.recalc_rate = xvcu_pll_recalc_rate, |
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.set_rate = xvcu_pll_set_rate, |
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}; |
|
|
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static struct clk_hw *xvcu_register_pll(struct device *dev, |
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void __iomem *reg_base, |
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const char *name, const char *parent, |
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unsigned long flags) |
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{ |
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struct vcu_pll *pll; |
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struct clk_hw *hw; |
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struct clk_init_data init; |
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int ret; |
|
|
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init.name = name; |
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init.parent_names = &parent; |
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init.ops = &vcu_pll_ops; |
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init.num_parents = 1; |
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init.flags = flags; |
|
|
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pll = devm_kmalloc(dev, sizeof(*pll), GFP_KERNEL); |
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if (!pll) |
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return ERR_PTR(-ENOMEM); |
|
|
|
pll->hw.init = &init; |
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pll->reg_base = reg_base; |
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pll->fvco_min = FVCO_MIN; |
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pll->fvco_max = FVCO_MAX; |
|
|
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hw = &pll->hw; |
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ret = devm_clk_hw_register(dev, hw); |
|
if (ret) |
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return ERR_PTR(ret); |
|
|
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clk_hw_set_rate_range(hw, pll->fvco_min, pll->fvco_max); |
|
|
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return hw; |
|
} |
|
|
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static struct clk_hw *xvcu_clk_hw_register_leaf(struct device *dev, |
|
const char *name, |
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const struct clk_parent_data *parent_data, |
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u8 num_parents, |
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void __iomem *reg) |
|
{ |
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u8 mux_flags = CLK_MUX_ROUND_CLOSEST; |
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u8 divider_flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO | |
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CLK_DIVIDER_ROUND_CLOSEST; |
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struct clk_hw *mux = NULL; |
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struct clk_hw *divider = NULL; |
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struct clk_hw *gate = NULL; |
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char *name_mux; |
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char *name_div; |
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int err; |
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/* Protect register shared by clocks */ |
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spinlock_t *lock; |
|
|
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lock = devm_kzalloc(dev, sizeof(*lock), GFP_KERNEL); |
|
if (!lock) |
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return ERR_PTR(-ENOMEM); |
|
spin_lock_init(lock); |
|
|
|
name_mux = devm_kasprintf(dev, GFP_KERNEL, "%s%s", name, "_mux"); |
|
if (!name_mux) |
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return ERR_PTR(-ENOMEM); |
|
mux = clk_hw_register_mux_parent_data(dev, name_mux, |
|
parent_data, num_parents, |
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CLK_SET_RATE_PARENT, |
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reg, 0, 1, mux_flags, lock); |
|
if (IS_ERR(mux)) |
|
return mux; |
|
|
|
name_div = devm_kasprintf(dev, GFP_KERNEL, "%s%s", name, "_div"); |
|
if (!name_div) { |
|
err = -ENOMEM; |
|
goto unregister_mux; |
|
} |
|
divider = clk_hw_register_divider_parent_hw(dev, name_div, mux, |
|
CLK_SET_RATE_PARENT, |
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reg, 4, 6, divider_flags, |
|
lock); |
|
if (IS_ERR(divider)) { |
|
err = PTR_ERR(divider); |
|
goto unregister_mux; |
|
} |
|
|
|
gate = clk_hw_register_gate_parent_hw(dev, name, divider, |
|
CLK_SET_RATE_PARENT, reg, 12, 0, |
|
lock); |
|
if (IS_ERR(gate)) { |
|
err = PTR_ERR(gate); |
|
goto unregister_divider; |
|
} |
|
|
|
return gate; |
|
|
|
unregister_divider: |
|
clk_hw_unregister_divider(divider); |
|
unregister_mux: |
|
clk_hw_unregister_mux(mux); |
|
|
|
return ERR_PTR(err); |
|
} |
|
|
|
static void xvcu_clk_hw_unregister_leaf(struct clk_hw *hw) |
|
{ |
|
struct clk_hw *gate = hw; |
|
struct clk_hw *divider; |
|
struct clk_hw *mux; |
|
|
|
if (!gate) |
|
return; |
|
|
|
divider = clk_hw_get_parent(gate); |
|
clk_hw_unregister_gate(gate); |
|
if (!divider) |
|
return; |
|
|
|
mux = clk_hw_get_parent(divider); |
|
clk_hw_unregister_mux(mux); |
|
if (!divider) |
|
return; |
|
|
|
clk_hw_unregister_divider(divider); |
|
} |
|
|
|
static int xvcu_register_clock_provider(struct xvcu_device *xvcu) |
|
{ |
|
struct device *dev = xvcu->dev; |
|
struct clk_parent_data parent_data[2] = { 0 }; |
|
struct clk_hw_onecell_data *data; |
|
struct clk_hw **hws; |
|
struct clk_hw *hw; |
|
void __iomem *reg_base = xvcu->vcu_slcr_ba; |
|
|
|
data = devm_kzalloc(dev, struct_size(data, hws, CLK_XVCU_NUM_CLOCKS), GFP_KERNEL); |
|
if (!data) |
|
return -ENOMEM; |
|
data->num = CLK_XVCU_NUM_CLOCKS; |
|
hws = data->hws; |
|
|
|
xvcu->clk_data = data; |
|
|
|
hw = xvcu_register_pll(dev, reg_base, |
|
"vcu_pll", __clk_get_name(xvcu->pll_ref), |
|
CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
xvcu->pll = hw; |
|
|
|
hw = xvcu_register_pll_post(dev, "vcu_pll_post", xvcu->pll, reg_base); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
xvcu->pll_post = hw; |
|
|
|
parent_data[0].fw_name = "pll_ref"; |
|
parent_data[1].hw = xvcu->pll_post; |
|
|
|
hws[CLK_XVCU_ENC_CORE] = |
|
xvcu_clk_hw_register_leaf(dev, "venc_core_clk", |
|
parent_data, |
|
ARRAY_SIZE(parent_data), |
|
reg_base + VCU_ENC_CORE_CTRL); |
|
hws[CLK_XVCU_ENC_MCU] = |
|
xvcu_clk_hw_register_leaf(dev, "venc_mcu_clk", |
|
parent_data, |
|
ARRAY_SIZE(parent_data), |
|
reg_base + VCU_ENC_MCU_CTRL); |
|
hws[CLK_XVCU_DEC_CORE] = |
|
xvcu_clk_hw_register_leaf(dev, "vdec_core_clk", |
|
parent_data, |
|
ARRAY_SIZE(parent_data), |
|
reg_base + VCU_DEC_CORE_CTRL); |
|
hws[CLK_XVCU_DEC_MCU] = |
|
xvcu_clk_hw_register_leaf(dev, "vdec_mcu_clk", |
|
parent_data, |
|
ARRAY_SIZE(parent_data), |
|
reg_base + VCU_DEC_MCU_CTRL); |
|
|
|
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data); |
|
} |
|
|
|
static void xvcu_unregister_clock_provider(struct xvcu_device *xvcu) |
|
{ |
|
struct clk_hw_onecell_data *data = xvcu->clk_data; |
|
struct clk_hw **hws = data->hws; |
|
|
|
if (!IS_ERR_OR_NULL(hws[CLK_XVCU_DEC_MCU])) |
|
xvcu_clk_hw_unregister_leaf(hws[CLK_XVCU_DEC_MCU]); |
|
if (!IS_ERR_OR_NULL(hws[CLK_XVCU_DEC_CORE])) |
|
xvcu_clk_hw_unregister_leaf(hws[CLK_XVCU_DEC_CORE]); |
|
if (!IS_ERR_OR_NULL(hws[CLK_XVCU_ENC_MCU])) |
|
xvcu_clk_hw_unregister_leaf(hws[CLK_XVCU_ENC_MCU]); |
|
if (!IS_ERR_OR_NULL(hws[CLK_XVCU_ENC_CORE])) |
|
xvcu_clk_hw_unregister_leaf(hws[CLK_XVCU_ENC_CORE]); |
|
|
|
clk_hw_unregister_fixed_factor(xvcu->pll_post); |
|
} |
|
|
|
/** |
|
* xvcu_probe - Probe existence of the logicoreIP |
|
* and initialize PLL |
|
* |
|
* @pdev: Pointer to the platform_device structure |
|
* |
|
* Return: Returns 0 on success |
|
* Negative error code otherwise |
|
*/ |
|
static int xvcu_probe(struct platform_device *pdev) |
|
{ |
|
struct resource *res; |
|
struct xvcu_device *xvcu; |
|
void __iomem *regs; |
|
int ret; |
|
|
|
xvcu = devm_kzalloc(&pdev->dev, sizeof(*xvcu), GFP_KERNEL); |
|
if (!xvcu) |
|
return -ENOMEM; |
|
|
|
xvcu->dev = &pdev->dev; |
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vcu_slcr"); |
|
if (!res) { |
|
dev_err(&pdev->dev, "get vcu_slcr memory resource failed.\n"); |
|
return -ENODEV; |
|
} |
|
|
|
xvcu->vcu_slcr_ba = devm_ioremap(&pdev->dev, res->start, |
|
resource_size(res)); |
|
if (!xvcu->vcu_slcr_ba) { |
|
dev_err(&pdev->dev, "vcu_slcr register mapping failed.\n"); |
|
return -ENOMEM; |
|
} |
|
|
|
xvcu->logicore_reg_ba = |
|
syscon_regmap_lookup_by_compatible("xlnx,vcu-settings"); |
|
if (IS_ERR(xvcu->logicore_reg_ba)) { |
|
dev_info(&pdev->dev, |
|
"could not find xlnx,vcu-settings: trying direct register access\n"); |
|
|
|
res = platform_get_resource_byname(pdev, |
|
IORESOURCE_MEM, "logicore"); |
|
if (!res) { |
|
dev_err(&pdev->dev, "get logicore memory resource failed.\n"); |
|
return -ENODEV; |
|
} |
|
|
|
regs = devm_ioremap(&pdev->dev, res->start, resource_size(res)); |
|
if (!regs) { |
|
dev_err(&pdev->dev, "logicore register mapping failed.\n"); |
|
return -ENOMEM; |
|
} |
|
|
|
xvcu->logicore_reg_ba = |
|
devm_regmap_init_mmio(&pdev->dev, regs, |
|
&vcu_settings_regmap_config); |
|
if (IS_ERR(xvcu->logicore_reg_ba)) { |
|
dev_err(&pdev->dev, "failed to init regmap\n"); |
|
return PTR_ERR(xvcu->logicore_reg_ba); |
|
} |
|
} |
|
|
|
xvcu->aclk = devm_clk_get(&pdev->dev, "aclk"); |
|
if (IS_ERR(xvcu->aclk)) { |
|
dev_err(&pdev->dev, "Could not get aclk clock\n"); |
|
return PTR_ERR(xvcu->aclk); |
|
} |
|
|
|
xvcu->pll_ref = devm_clk_get(&pdev->dev, "pll_ref"); |
|
if (IS_ERR(xvcu->pll_ref)) { |
|
dev_err(&pdev->dev, "Could not get pll_ref clock\n"); |
|
return PTR_ERR(xvcu->pll_ref); |
|
} |
|
|
|
ret = clk_prepare_enable(xvcu->aclk); |
|
if (ret) { |
|
dev_err(&pdev->dev, "aclk clock enable failed\n"); |
|
return ret; |
|
} |
|
|
|
/* |
|
* Do the Gasket isolation and put the VCU out of reset |
|
* Bit 0 : Gasket isolation |
|
* Bit 1 : put VCU out of reset |
|
*/ |
|
regmap_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, VCU_GASKET_VALUE); |
|
|
|
ret = xvcu_register_clock_provider(xvcu); |
|
if (ret) { |
|
dev_err(&pdev->dev, "failed to register clock provider\n"); |
|
goto error_clk_provider; |
|
} |
|
|
|
dev_set_drvdata(&pdev->dev, xvcu); |
|
|
|
return 0; |
|
|
|
error_clk_provider: |
|
xvcu_unregister_clock_provider(xvcu); |
|
clk_disable_unprepare(xvcu->aclk); |
|
return ret; |
|
} |
|
|
|
/** |
|
* xvcu_remove - Insert gasket isolation |
|
* and disable the clock |
|
* @pdev: Pointer to the platform_device structure |
|
* |
|
* Return: Returns 0 on success |
|
* Negative error code otherwise |
|
*/ |
|
static int xvcu_remove(struct platform_device *pdev) |
|
{ |
|
struct xvcu_device *xvcu; |
|
|
|
xvcu = platform_get_drvdata(pdev); |
|
if (!xvcu) |
|
return -ENODEV; |
|
|
|
xvcu_unregister_clock_provider(xvcu); |
|
|
|
/* Add the Gasket isolation and put the VCU in reset. */ |
|
regmap_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, 0); |
|
|
|
clk_disable_unprepare(xvcu->aclk); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id xvcu_of_id_table[] = { |
|
{ .compatible = "xlnx,vcu" }, |
|
{ .compatible = "xlnx,vcu-logicoreip-1.0" }, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, xvcu_of_id_table); |
|
|
|
static struct platform_driver xvcu_driver = { |
|
.driver = { |
|
.name = "xilinx-vcu", |
|
.of_match_table = xvcu_of_id_table, |
|
}, |
|
.probe = xvcu_probe, |
|
.remove = xvcu_remove, |
|
}; |
|
|
|
module_platform_driver(xvcu_driver); |
|
|
|
MODULE_AUTHOR("Dhaval Shah <[email protected]>"); |
|
MODULE_DESCRIPTION("Xilinx VCU init Driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|