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287 lines
6.9 KiB
287 lines
6.9 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2016 Maxime Ripard |
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* Maxime Ripard <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include "ccu_gate.h" |
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#include "ccu_mux.h" |
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static u16 ccu_mux_get_prediv(struct ccu_common *common, |
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struct ccu_mux_internal *cm, |
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int parent_index) |
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{ |
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u16 prediv = 1; |
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u32 reg; |
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if (!((common->features & CCU_FEATURE_FIXED_PREDIV) || |
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(common->features & CCU_FEATURE_VARIABLE_PREDIV) || |
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(common->features & CCU_FEATURE_ALL_PREDIV))) |
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return 1; |
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if (common->features & CCU_FEATURE_ALL_PREDIV) |
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return common->prediv; |
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reg = readl(common->base + common->reg); |
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if (parent_index < 0) { |
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parent_index = reg >> cm->shift; |
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parent_index &= (1 << cm->width) - 1; |
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} |
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if (common->features & CCU_FEATURE_FIXED_PREDIV) { |
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int i; |
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for (i = 0; i < cm->n_predivs; i++) |
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if (parent_index == cm->fixed_predivs[i].index) |
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prediv = cm->fixed_predivs[i].div; |
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} |
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if (common->features & CCU_FEATURE_VARIABLE_PREDIV) { |
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int i; |
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for (i = 0; i < cm->n_var_predivs; i++) |
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if (parent_index == cm->var_predivs[i].index) { |
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u8 div; |
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div = reg >> cm->var_predivs[i].shift; |
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div &= (1 << cm->var_predivs[i].width) - 1; |
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prediv = div + 1; |
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} |
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} |
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return prediv; |
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} |
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unsigned long ccu_mux_helper_apply_prediv(struct ccu_common *common, |
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struct ccu_mux_internal *cm, |
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int parent_index, |
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unsigned long parent_rate) |
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{ |
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return parent_rate / ccu_mux_get_prediv(common, cm, parent_index); |
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} |
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static unsigned long ccu_mux_helper_unapply_prediv(struct ccu_common *common, |
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struct ccu_mux_internal *cm, |
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int parent_index, |
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unsigned long parent_rate) |
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{ |
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return parent_rate * ccu_mux_get_prediv(common, cm, parent_index); |
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} |
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int ccu_mux_helper_determine_rate(struct ccu_common *common, |
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struct ccu_mux_internal *cm, |
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struct clk_rate_request *req, |
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unsigned long (*round)(struct ccu_mux_internal *, |
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struct clk_hw *, |
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unsigned long *, |
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unsigned long, |
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void *), |
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void *data) |
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{ |
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unsigned long best_parent_rate = 0, best_rate = 0; |
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struct clk_hw *best_parent, *hw = &common->hw; |
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unsigned int i; |
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) { |
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unsigned long adj_parent_rate; |
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best_parent = clk_hw_get_parent(hw); |
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best_parent_rate = clk_hw_get_rate(best_parent); |
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adj_parent_rate = ccu_mux_helper_apply_prediv(common, cm, -1, |
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best_parent_rate); |
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best_rate = round(cm, best_parent, &adj_parent_rate, |
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req->rate, data); |
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/* |
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* adj_parent_rate might have been modified by our clock. |
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* Unapply the pre-divider if there's one, and give |
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* the actual frequency the parent needs to run at. |
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*/ |
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best_parent_rate = ccu_mux_helper_unapply_prediv(common, cm, -1, |
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adj_parent_rate); |
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goto out; |
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} |
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for (i = 0; i < clk_hw_get_num_parents(hw); i++) { |
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unsigned long tmp_rate, parent_rate; |
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struct clk_hw *parent; |
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parent = clk_hw_get_parent_by_index(hw, i); |
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if (!parent) |
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continue; |
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parent_rate = ccu_mux_helper_apply_prediv(common, cm, i, |
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clk_hw_get_rate(parent)); |
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tmp_rate = round(cm, parent, &parent_rate, req->rate, data); |
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/* |
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* parent_rate might have been modified by our clock. |
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* Unapply the pre-divider if there's one, and give |
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* the actual frequency the parent needs to run at. |
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*/ |
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parent_rate = ccu_mux_helper_unapply_prediv(common, cm, i, |
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parent_rate); |
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if (tmp_rate == req->rate) { |
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best_parent = parent; |
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best_parent_rate = parent_rate; |
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best_rate = tmp_rate; |
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goto out; |
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} |
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if ((req->rate - tmp_rate) < (req->rate - best_rate)) { |
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best_rate = tmp_rate; |
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best_parent_rate = parent_rate; |
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best_parent = parent; |
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} |
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} |
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if (best_rate == 0) |
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return -EINVAL; |
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out: |
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req->best_parent_hw = best_parent; |
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req->best_parent_rate = best_parent_rate; |
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req->rate = best_rate; |
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return 0; |
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} |
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u8 ccu_mux_helper_get_parent(struct ccu_common *common, |
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struct ccu_mux_internal *cm) |
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{ |
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u32 reg; |
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u8 parent; |
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reg = readl(common->base + common->reg); |
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parent = reg >> cm->shift; |
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parent &= (1 << cm->width) - 1; |
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if (cm->table) { |
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int num_parents = clk_hw_get_num_parents(&common->hw); |
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int i; |
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for (i = 0; i < num_parents; i++) |
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if (cm->table[i] == parent) |
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return i; |
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} |
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return parent; |
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} |
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int ccu_mux_helper_set_parent(struct ccu_common *common, |
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struct ccu_mux_internal *cm, |
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u8 index) |
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{ |
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unsigned long flags; |
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u32 reg; |
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if (cm->table) |
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index = cm->table[index]; |
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spin_lock_irqsave(common->lock, flags); |
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reg = readl(common->base + common->reg); |
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reg &= ~GENMASK(cm->width + cm->shift - 1, cm->shift); |
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writel(reg | (index << cm->shift), common->base + common->reg); |
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spin_unlock_irqrestore(common->lock, flags); |
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return 0; |
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} |
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static void ccu_mux_disable(struct clk_hw *hw) |
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{ |
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struct ccu_mux *cm = hw_to_ccu_mux(hw); |
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return ccu_gate_helper_disable(&cm->common, cm->enable); |
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} |
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static int ccu_mux_enable(struct clk_hw *hw) |
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{ |
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struct ccu_mux *cm = hw_to_ccu_mux(hw); |
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return ccu_gate_helper_enable(&cm->common, cm->enable); |
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} |
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static int ccu_mux_is_enabled(struct clk_hw *hw) |
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{ |
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struct ccu_mux *cm = hw_to_ccu_mux(hw); |
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return ccu_gate_helper_is_enabled(&cm->common, cm->enable); |
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} |
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static u8 ccu_mux_get_parent(struct clk_hw *hw) |
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{ |
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struct ccu_mux *cm = hw_to_ccu_mux(hw); |
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return ccu_mux_helper_get_parent(&cm->common, &cm->mux); |
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} |
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static int ccu_mux_set_parent(struct clk_hw *hw, u8 index) |
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{ |
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struct ccu_mux *cm = hw_to_ccu_mux(hw); |
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return ccu_mux_helper_set_parent(&cm->common, &cm->mux, index); |
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} |
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static unsigned long ccu_mux_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct ccu_mux *cm = hw_to_ccu_mux(hw); |
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return ccu_mux_helper_apply_prediv(&cm->common, &cm->mux, -1, |
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parent_rate); |
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} |
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const struct clk_ops ccu_mux_ops = { |
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.disable = ccu_mux_disable, |
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.enable = ccu_mux_enable, |
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.is_enabled = ccu_mux_is_enabled, |
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.get_parent = ccu_mux_get_parent, |
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.set_parent = ccu_mux_set_parent, |
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.determine_rate = __clk_mux_determine_rate, |
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.recalc_rate = ccu_mux_recalc_rate, |
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}; |
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/* |
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* This clock notifier is called when the frequency of the of the parent |
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* PLL clock is to be changed. The idea is to switch the parent to a |
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* stable clock, such as the main oscillator, while the PLL frequency |
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* stabilizes. |
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*/ |
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static int ccu_mux_notifier_cb(struct notifier_block *nb, |
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unsigned long event, void *data) |
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{ |
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struct ccu_mux_nb *mux = to_ccu_mux_nb(nb); |
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int ret = 0; |
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if (event == PRE_RATE_CHANGE) { |
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mux->original_index = ccu_mux_helper_get_parent(mux->common, |
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mux->cm); |
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ret = ccu_mux_helper_set_parent(mux->common, mux->cm, |
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mux->bypass_index); |
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} else if (event == POST_RATE_CHANGE) { |
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ret = ccu_mux_helper_set_parent(mux->common, mux->cm, |
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mux->original_index); |
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} |
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udelay(mux->delay_us); |
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return notifier_from_errno(ret); |
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} |
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int ccu_mux_notifier_register(struct clk *clk, struct ccu_mux_nb *mux_nb) |
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{ |
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mux_nb->clk_nb.notifier_call = ccu_mux_notifier_cb; |
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return clk_notifier_register(clk, &mux_nb->clk_nb); |
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}
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