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275 lines
8.0 KiB
275 lines
8.0 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2016 Chen-Yu Tsai. All rights reserved. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/of_address.h> |
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#include <linux/platform_device.h> |
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#include <linux/reset.h> |
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#include "ccu_common.h" |
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#include "ccu_div.h" |
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#include "ccu_gate.h" |
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#include "ccu_reset.h" |
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#include "ccu-sun9i-a80-de.h" |
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static SUNXI_CCU_GATE(fe0_clk, "fe0", "fe0-div", |
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0x00, BIT(0), 0); |
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static SUNXI_CCU_GATE(fe1_clk, "fe1", "fe1-div", |
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0x00, BIT(1), 0); |
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static SUNXI_CCU_GATE(fe2_clk, "fe2", "fe2-div", |
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0x00, BIT(2), 0); |
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static SUNXI_CCU_GATE(iep_deu0_clk, "iep-deu0", "de", |
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0x00, BIT(4), 0); |
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static SUNXI_CCU_GATE(iep_deu1_clk, "iep-deu1", "de", |
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0x00, BIT(5), 0); |
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static SUNXI_CCU_GATE(be0_clk, "be0", "be0-div", |
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0x00, BIT(8), 0); |
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static SUNXI_CCU_GATE(be1_clk, "be1", "be1-div", |
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0x00, BIT(9), 0); |
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static SUNXI_CCU_GATE(be2_clk, "be2", "be2-div", |
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0x00, BIT(10), 0); |
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static SUNXI_CCU_GATE(iep_drc0_clk, "iep-drc0", "de", |
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0x00, BIT(12), 0); |
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static SUNXI_CCU_GATE(iep_drc1_clk, "iep-drc1", "de", |
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0x00, BIT(13), 0); |
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static SUNXI_CCU_GATE(merge_clk, "merge", "de", |
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0x00, BIT(20), 0); |
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static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "sdram", |
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0x04, BIT(0), 0); |
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static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "sdram", |
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0x04, BIT(1), 0); |
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static SUNXI_CCU_GATE(dram_fe2_clk, "dram-fe2", "sdram", |
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0x04, BIT(2), 0); |
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static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "sdram", |
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0x04, BIT(4), 0); |
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static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "sdram", |
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0x04, BIT(5), 0); |
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static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "sdram", |
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0x04, BIT(8), 0); |
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static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "sdram", |
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0x04, BIT(9), 0); |
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static SUNXI_CCU_GATE(dram_be2_clk, "dram-be2", "sdram", |
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0x04, BIT(10), 0); |
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static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "sdram", |
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0x04, BIT(12), 0); |
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static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "sdram", |
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0x04, BIT(13), 0); |
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static SUNXI_CCU_GATE(bus_fe0_clk, "bus-fe0", "bus-de", |
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0x08, BIT(0), 0); |
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static SUNXI_CCU_GATE(bus_fe1_clk, "bus-fe1", "bus-de", |
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0x08, BIT(1), 0); |
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static SUNXI_CCU_GATE(bus_fe2_clk, "bus-fe2", "bus-de", |
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0x08, BIT(2), 0); |
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static SUNXI_CCU_GATE(bus_deu0_clk, "bus-deu0", "bus-de", |
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0x08, BIT(4), 0); |
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static SUNXI_CCU_GATE(bus_deu1_clk, "bus-deu1", "bus-de", |
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0x08, BIT(5), 0); |
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static SUNXI_CCU_GATE(bus_be0_clk, "bus-be0", "bus-de", |
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0x08, BIT(8), 0); |
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static SUNXI_CCU_GATE(bus_be1_clk, "bus-be1", "bus-de", |
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0x08, BIT(9), 0); |
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static SUNXI_CCU_GATE(bus_be2_clk, "bus-be2", "bus-de", |
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0x08, BIT(10), 0); |
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static SUNXI_CCU_GATE(bus_drc0_clk, "bus-drc0", "bus-de", |
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0x08, BIT(12), 0); |
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static SUNXI_CCU_GATE(bus_drc1_clk, "bus-drc1", "bus-de", |
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0x08, BIT(13), 0); |
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static SUNXI_CCU_M(fe0_div_clk, "fe0-div", "de", 0x20, 0, 4, 0); |
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static SUNXI_CCU_M(fe1_div_clk, "fe1-div", "de", 0x20, 4, 4, 0); |
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static SUNXI_CCU_M(fe2_div_clk, "fe2-div", "de", 0x20, 8, 4, 0); |
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static SUNXI_CCU_M(be0_div_clk, "be0-div", "de", 0x20, 16, 4, 0); |
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static SUNXI_CCU_M(be1_div_clk, "be1-div", "de", 0x20, 20, 4, 0); |
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static SUNXI_CCU_M(be2_div_clk, "be2-div", "de", 0x20, 24, 4, 0); |
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static struct ccu_common *sun9i_a80_de_clks[] = { |
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&fe0_clk.common, |
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&fe1_clk.common, |
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&fe2_clk.common, |
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&iep_deu0_clk.common, |
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&iep_deu1_clk.common, |
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&be0_clk.common, |
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&be1_clk.common, |
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&be2_clk.common, |
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&iep_drc0_clk.common, |
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&iep_drc1_clk.common, |
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&merge_clk.common, |
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&dram_fe0_clk.common, |
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&dram_fe1_clk.common, |
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&dram_fe2_clk.common, |
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&dram_deu0_clk.common, |
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&dram_deu1_clk.common, |
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&dram_be0_clk.common, |
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&dram_be1_clk.common, |
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&dram_be2_clk.common, |
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&dram_drc0_clk.common, |
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&dram_drc1_clk.common, |
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&bus_fe0_clk.common, |
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&bus_fe1_clk.common, |
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&bus_fe2_clk.common, |
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&bus_deu0_clk.common, |
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&bus_deu1_clk.common, |
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&bus_be0_clk.common, |
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&bus_be1_clk.common, |
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&bus_be2_clk.common, |
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&bus_drc0_clk.common, |
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&bus_drc1_clk.common, |
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&fe0_div_clk.common, |
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&fe1_div_clk.common, |
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&fe2_div_clk.common, |
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&be0_div_clk.common, |
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&be1_div_clk.common, |
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&be2_div_clk.common, |
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}; |
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static struct clk_hw_onecell_data sun9i_a80_de_hw_clks = { |
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.hws = { |
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[CLK_FE0] = &fe0_clk.common.hw, |
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[CLK_FE1] = &fe1_clk.common.hw, |
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[CLK_FE2] = &fe2_clk.common.hw, |
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[CLK_IEP_DEU0] = &iep_deu0_clk.common.hw, |
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[CLK_IEP_DEU1] = &iep_deu1_clk.common.hw, |
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[CLK_BE0] = &be0_clk.common.hw, |
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[CLK_BE1] = &be1_clk.common.hw, |
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[CLK_BE2] = &be2_clk.common.hw, |
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[CLK_IEP_DRC0] = &iep_drc0_clk.common.hw, |
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[CLK_IEP_DRC1] = &iep_drc1_clk.common.hw, |
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[CLK_MERGE] = &merge_clk.common.hw, |
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[CLK_DRAM_FE0] = &dram_fe0_clk.common.hw, |
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[CLK_DRAM_FE1] = &dram_fe1_clk.common.hw, |
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[CLK_DRAM_FE2] = &dram_fe2_clk.common.hw, |
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[CLK_DRAM_DEU0] = &dram_deu0_clk.common.hw, |
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[CLK_DRAM_DEU1] = &dram_deu1_clk.common.hw, |
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[CLK_DRAM_BE0] = &dram_be0_clk.common.hw, |
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[CLK_DRAM_BE1] = &dram_be1_clk.common.hw, |
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[CLK_DRAM_BE2] = &dram_be2_clk.common.hw, |
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[CLK_DRAM_DRC0] = &dram_drc0_clk.common.hw, |
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[CLK_DRAM_DRC1] = &dram_drc1_clk.common.hw, |
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[CLK_BUS_FE0] = &bus_fe0_clk.common.hw, |
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[CLK_BUS_FE1] = &bus_fe1_clk.common.hw, |
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[CLK_BUS_FE2] = &bus_fe2_clk.common.hw, |
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[CLK_BUS_DEU0] = &bus_deu0_clk.common.hw, |
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[CLK_BUS_DEU1] = &bus_deu1_clk.common.hw, |
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[CLK_BUS_BE0] = &bus_be0_clk.common.hw, |
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[CLK_BUS_BE1] = &bus_be1_clk.common.hw, |
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[CLK_BUS_BE2] = &bus_be2_clk.common.hw, |
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[CLK_BUS_DRC0] = &bus_drc0_clk.common.hw, |
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[CLK_BUS_DRC1] = &bus_drc1_clk.common.hw, |
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[CLK_FE0_DIV] = &fe0_div_clk.common.hw, |
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[CLK_FE1_DIV] = &fe1_div_clk.common.hw, |
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[CLK_FE2_DIV] = &fe2_div_clk.common.hw, |
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[CLK_BE0_DIV] = &be0_div_clk.common.hw, |
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[CLK_BE1_DIV] = &be1_div_clk.common.hw, |
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[CLK_BE2_DIV] = &be2_div_clk.common.hw, |
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}, |
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.num = CLK_NUMBER, |
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}; |
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static struct ccu_reset_map sun9i_a80_de_resets[] = { |
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[RST_FE0] = { 0x0c, BIT(0) }, |
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[RST_FE1] = { 0x0c, BIT(1) }, |
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[RST_FE2] = { 0x0c, BIT(2) }, |
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[RST_DEU0] = { 0x0c, BIT(4) }, |
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[RST_DEU1] = { 0x0c, BIT(5) }, |
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[RST_BE0] = { 0x0c, BIT(8) }, |
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[RST_BE1] = { 0x0c, BIT(9) }, |
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[RST_BE2] = { 0x0c, BIT(10) }, |
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[RST_DRC0] = { 0x0c, BIT(12) }, |
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[RST_DRC1] = { 0x0c, BIT(13) }, |
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[RST_MERGE] = { 0x0c, BIT(20) }, |
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}; |
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static const struct sunxi_ccu_desc sun9i_a80_de_clk_desc = { |
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.ccu_clks = sun9i_a80_de_clks, |
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.num_ccu_clks = ARRAY_SIZE(sun9i_a80_de_clks), |
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.hw_clks = &sun9i_a80_de_hw_clks, |
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.resets = sun9i_a80_de_resets, |
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.num_resets = ARRAY_SIZE(sun9i_a80_de_resets), |
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}; |
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static int sun9i_a80_de_clk_probe(struct platform_device *pdev) |
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{ |
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struct resource *res; |
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struct clk *bus_clk; |
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struct reset_control *rstc; |
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void __iomem *reg; |
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int ret; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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reg = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(reg)) |
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return PTR_ERR(reg); |
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bus_clk = devm_clk_get(&pdev->dev, "bus"); |
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if (IS_ERR(bus_clk)) { |
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ret = PTR_ERR(bus_clk); |
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if (ret != -EPROBE_DEFER) |
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dev_err(&pdev->dev, "Couldn't get bus clk: %d\n", ret); |
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return ret; |
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} |
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rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); |
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if (IS_ERR(rstc)) { |
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ret = PTR_ERR(rstc); |
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if (ret != -EPROBE_DEFER) |
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dev_err(&pdev->dev, |
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"Couldn't get reset control: %d\n", ret); |
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return ret; |
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} |
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/* The bus clock needs to be enabled for us to access the registers */ |
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ret = clk_prepare_enable(bus_clk); |
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if (ret) { |
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dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret); |
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return ret; |
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} |
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/* The reset control needs to be asserted for the controls to work */ |
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ret = reset_control_deassert(rstc); |
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if (ret) { |
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dev_err(&pdev->dev, |
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"Couldn't deassert reset control: %d\n", ret); |
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goto err_disable_clk; |
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} |
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ret = sunxi_ccu_probe(pdev->dev.of_node, reg, |
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&sun9i_a80_de_clk_desc); |
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if (ret) |
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goto err_assert_reset; |
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return 0; |
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err_assert_reset: |
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reset_control_assert(rstc); |
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err_disable_clk: |
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clk_disable_unprepare(bus_clk); |
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return ret; |
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} |
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static const struct of_device_id sun9i_a80_de_clk_ids[] = { |
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{ .compatible = "allwinner,sun9i-a80-de-clks" }, |
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{ } |
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}; |
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static struct platform_driver sun9i_a80_de_clk_driver = { |
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.probe = sun9i_a80_de_clk_probe, |
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.driver = { |
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.name = "sun9i-a80-de-clks", |
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.of_match_table = sun9i_a80_de_clk_ids, |
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}, |
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}; |
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builtin_platform_driver(sun9i_a80_de_clk_driver);
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