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52 lines
1.3 KiB
52 lines
1.3 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* Copyright 2017 Priit Laes |
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* |
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* Priit Laes <[email protected]> |
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*/ |
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#ifndef _CCU_SUN4I_A10_H_ |
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#define _CCU_SUN4I_A10_H_ |
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#include <dt-bindings/clock/sun4i-a10-ccu.h> |
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#include <dt-bindings/clock/sun7i-a20-ccu.h> |
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#include <dt-bindings/reset/sun4i-a10-ccu.h> |
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/* The HOSC is exported */ |
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#define CLK_PLL_CORE 2 |
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#define CLK_PLL_AUDIO_BASE 3 |
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#define CLK_PLL_AUDIO 4 |
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#define CLK_PLL_AUDIO_2X 5 |
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#define CLK_PLL_AUDIO_4X 6 |
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#define CLK_PLL_AUDIO_8X 7 |
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#define CLK_PLL_VIDEO0 8 |
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/* The PLL_VIDEO0_2X clock is exported */ |
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#define CLK_PLL_VE 10 |
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#define CLK_PLL_DDR_BASE 11 |
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#define CLK_PLL_DDR 12 |
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#define CLK_PLL_DDR_OTHER 13 |
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#define CLK_PLL_PERIPH_BASE 14 |
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#define CLK_PLL_PERIPH 15 |
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#define CLK_PLL_PERIPH_SATA 16 |
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#define CLK_PLL_VIDEO1 17 |
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/* The PLL_VIDEO1_2X clock is exported */ |
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#define CLK_PLL_GPU 19 |
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/* The CPU clock is exported */ |
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#define CLK_AXI 21 |
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#define CLK_AXI_DRAM 22 |
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#define CLK_AHB 23 |
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#define CLK_APB0 24 |
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#define CLK_APB1 25 |
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/* AHB gates are exported (23..68) */ |
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/* APB0 gates are exported (69..78) */ |
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/* APB1 gates are exported (79..95) */ |
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/* IP module clocks are exported (96..128) */ |
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/* DRAM gates are exported (129..142)*/ |
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/* Media (display engine clocks & etc) are exported (143..169) */ |
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#define CLK_NUMBER_SUN4I (CLK_MBUS + 1) |
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#define CLK_NUMBER_SUN7I (CLK_OUT_B + 1) |
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#endif /* _CCU_SUN4I_A10_H_ */
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