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134 lines
3.1 KiB
134 lines
3.1 KiB
/* |
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* Clock framework definitions for SPEAr platform |
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* |
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* Copyright (C) 2012 ST Microelectronics |
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* Viresh Kumar <[email protected]> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#ifndef __SPEAR_CLK_H |
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#define __SPEAR_CLK_H |
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#include <linux/clk-provider.h> |
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#include <linux/spinlock_types.h> |
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#include <linux/types.h> |
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/* Auxiliary Synth clk */ |
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/* Default masks */ |
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#define AUX_EQ_SEL_SHIFT 30 |
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#define AUX_EQ_SEL_MASK 1 |
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#define AUX_EQ1_SEL 0 |
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#define AUX_EQ2_SEL 1 |
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#define AUX_XSCALE_SHIFT 16 |
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#define AUX_XSCALE_MASK 0xFFF |
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#define AUX_YSCALE_SHIFT 0 |
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#define AUX_YSCALE_MASK 0xFFF |
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#define AUX_SYNT_ENB 31 |
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struct aux_clk_masks { |
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u32 eq_sel_mask; |
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u32 eq_sel_shift; |
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u32 eq1_mask; |
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u32 eq2_mask; |
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u32 xscale_sel_mask; |
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u32 xscale_sel_shift; |
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u32 yscale_sel_mask; |
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u32 yscale_sel_shift; |
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u32 enable_bit; |
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}; |
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struct aux_rate_tbl { |
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u16 xscale; |
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u16 yscale; |
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u8 eq; |
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}; |
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struct clk_aux { |
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struct clk_hw hw; |
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void __iomem *reg; |
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const struct aux_clk_masks *masks; |
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struct aux_rate_tbl *rtbl; |
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u8 rtbl_cnt; |
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spinlock_t *lock; |
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}; |
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/* Fractional Synth clk */ |
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struct frac_rate_tbl { |
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u32 div; |
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}; |
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struct clk_frac { |
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struct clk_hw hw; |
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void __iomem *reg; |
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struct frac_rate_tbl *rtbl; |
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u8 rtbl_cnt; |
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spinlock_t *lock; |
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}; |
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/* GPT clk */ |
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struct gpt_rate_tbl { |
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u16 mscale; |
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u16 nscale; |
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}; |
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struct clk_gpt { |
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struct clk_hw hw; |
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void __iomem *reg; |
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struct gpt_rate_tbl *rtbl; |
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u8 rtbl_cnt; |
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spinlock_t *lock; |
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}; |
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/* VCO-PLL clk */ |
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struct pll_rate_tbl { |
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u8 mode; |
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u16 m; |
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u8 n; |
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u8 p; |
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}; |
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struct clk_vco { |
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struct clk_hw hw; |
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void __iomem *mode_reg; |
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void __iomem *cfg_reg; |
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struct pll_rate_tbl *rtbl; |
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u8 rtbl_cnt; |
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spinlock_t *lock; |
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}; |
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struct clk_pll { |
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struct clk_hw hw; |
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struct clk_vco *vco; |
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const char *parent[1]; |
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spinlock_t *lock; |
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}; |
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typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate, |
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int index); |
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/* clk register routines */ |
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struct clk *clk_register_aux(const char *aux_name, const char *gate_name, |
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const char *parent_name, unsigned long flags, void __iomem *reg, |
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const struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, |
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u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk); |
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struct clk *clk_register_frac(const char *name, const char *parent_name, |
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unsigned long flags, void __iomem *reg, |
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struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock); |
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struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned |
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long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8 |
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rtbl_cnt, spinlock_t *lock); |
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struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name, |
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const char *vco_gate_name, const char *parent_name, |
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unsigned long flags, void __iomem *mode_reg, void __iomem |
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*cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, |
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spinlock_t *lock, struct clk **pll_clk, |
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struct clk **vco_gate_clk); |
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long clk_round_rate_index(struct clk_hw *hw, unsigned long drate, |
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unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt, |
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int *index); |
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#endif /* __SPEAR_CLK_H */
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