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232 lines
6.6 KiB
232 lines
6.6 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright 2014 Google, Inc |
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* Author: Alexandru M Stan <[email protected]> |
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*/ |
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#include <linux/slab.h> |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include "clk.h" |
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struct rockchip_mmc_clock { |
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struct clk_hw hw; |
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void __iomem *reg; |
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int id; |
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int shift; |
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int cached_phase; |
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struct notifier_block clk_rate_change_nb; |
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}; |
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#define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw) |
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#define RK3288_MMC_CLKGEN_DIV 2 |
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static unsigned long rockchip_mmc_recalc(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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return parent_rate / RK3288_MMC_CLKGEN_DIV; |
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} |
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#define ROCKCHIP_MMC_DELAY_SEL BIT(10) |
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#define ROCKCHIP_MMC_DEGREE_MASK 0x3 |
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#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 |
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#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) |
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#define PSECS_PER_SEC 1000000000000LL |
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/* |
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* Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to |
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* simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. |
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*/ |
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#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 |
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static int rockchip_mmc_get_phase(struct clk_hw *hw) |
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{ |
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struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw); |
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unsigned long rate = clk_hw_get_rate(hw); |
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u32 raw_value; |
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u16 degrees; |
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u32 delay_num = 0; |
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/* Constant signal, no measurable phase shift */ |
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if (!rate) |
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return 0; |
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raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); |
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degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; |
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if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { |
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/* degrees/delaynum * 1000000 */ |
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unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * |
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36 * (rate / 10000); |
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delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); |
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delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; |
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degrees += DIV_ROUND_CLOSEST(delay_num * factor, 1000000); |
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} |
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return degrees % 360; |
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} |
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static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees) |
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{ |
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struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw); |
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unsigned long rate = clk_hw_get_rate(hw); |
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u8 nineties, remainder; |
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u8 delay_num; |
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u32 raw_value; |
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u32 delay; |
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/* |
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* The below calculation is based on the output clock from |
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* MMC host to the card, which expects the phase clock inherits |
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* the clock rate from its parent, namely the output clock |
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* provider of MMC host. However, things may go wrong if |
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* (1) It is orphan. |
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* (2) It is assigned to the wrong parent. |
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* |
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* This check help debug the case (1), which seems to be the |
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* most likely problem we often face and which makes it difficult |
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* for people to debug unstable mmc tuning results. |
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*/ |
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if (!rate) { |
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pr_err("%s: invalid clk rate\n", __func__); |
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return -EINVAL; |
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} |
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nineties = degrees / 90; |
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remainder = (degrees % 90); |
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/* |
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* Due to the inexact nature of the "fine" delay, we might |
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* actually go non-monotonic. We don't go _too_ monotonic |
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* though, so we should be OK. Here are options of how we may |
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* work: |
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* |
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* Ideally we end up with: |
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* 1.0, 2.0, ..., 69.0, 70.0, ..., 89.0, 90.0 |
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* |
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* On one extreme (if delay is actually 44ps): |
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* .73, 1.5, ..., 50.6, 51.3, ..., 65.3, 90.0 |
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* The other (if delay is actually 77ps): |
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* 1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90 |
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* |
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* It's possible we might make a delay that is up to 25 |
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* degrees off from what we think we're making. That's OK |
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* though because we should be REALLY far from any bad range. |
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*/ |
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/* |
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* Convert to delay; do a little extra work to make sure we |
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* don't overflow 32-bit / 64-bit numbers. |
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*/ |
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delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ |
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delay *= remainder; |
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delay = DIV_ROUND_CLOSEST(delay, |
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(rate / 1000) * 36 * |
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(ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); |
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delay_num = (u8) min_t(u32, delay, 255); |
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raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; |
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raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; |
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raw_value |= nineties; |
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writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), |
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mmc_clock->reg); |
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pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n", |
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clk_hw_get_name(hw), degrees, delay_num, |
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mmc_clock->reg, raw_value>>(mmc_clock->shift), |
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rockchip_mmc_get_phase(hw) |
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); |
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return 0; |
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} |
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static const struct clk_ops rockchip_mmc_clk_ops = { |
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.recalc_rate = rockchip_mmc_recalc, |
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.get_phase = rockchip_mmc_get_phase, |
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.set_phase = rockchip_mmc_set_phase, |
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}; |
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#define to_rockchip_mmc_clock(x) \ |
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container_of(x, struct rockchip_mmc_clock, clk_rate_change_nb) |
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static int rockchip_mmc_clk_rate_notify(struct notifier_block *nb, |
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unsigned long event, void *data) |
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{ |
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struct rockchip_mmc_clock *mmc_clock = to_rockchip_mmc_clock(nb); |
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struct clk_notifier_data *ndata = data; |
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/* |
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* rockchip_mmc_clk is mostly used by mmc controllers to sample |
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* the intput data, which expects the fixed phase after the tuning |
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* process. However if the clock rate is changed, the phase is stale |
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* and may break the data sampling. So here we try to restore the phase |
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* for that case, except that |
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* (1) cached_phase is invaild since we inevitably cached it when the |
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* clock provider be reparented from orphan to its real parent in the |
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* first place. Otherwise we may mess up the initialization of MMC cards |
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* since we only set the default sample phase and drive phase later on. |
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* (2) the new coming rate is higher than the older one since mmc driver |
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* set the max-frequency to match the boards' ability but we can't go |
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* over the heads of that, otherwise the tests smoke out the issue. |
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*/ |
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if (ndata->old_rate <= ndata->new_rate) |
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return NOTIFY_DONE; |
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if (event == PRE_RATE_CHANGE) |
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mmc_clock->cached_phase = |
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rockchip_mmc_get_phase(&mmc_clock->hw); |
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else if (mmc_clock->cached_phase != -EINVAL && |
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event == POST_RATE_CHANGE) |
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rockchip_mmc_set_phase(&mmc_clock->hw, mmc_clock->cached_phase); |
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return NOTIFY_DONE; |
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} |
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struct clk *rockchip_clk_register_mmc(const char *name, |
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const char *const *parent_names, u8 num_parents, |
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void __iomem *reg, int shift) |
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{ |
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struct clk_init_data init; |
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struct rockchip_mmc_clock *mmc_clock; |
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struct clk *clk; |
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int ret; |
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mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL); |
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if (!mmc_clock) |
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return ERR_PTR(-ENOMEM); |
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init.name = name; |
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init.flags = 0; |
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init.num_parents = num_parents; |
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init.parent_names = parent_names; |
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init.ops = &rockchip_mmc_clk_ops; |
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mmc_clock->hw.init = &init; |
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mmc_clock->reg = reg; |
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mmc_clock->shift = shift; |
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clk = clk_register(NULL, &mmc_clock->hw); |
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if (IS_ERR(clk)) { |
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ret = PTR_ERR(clk); |
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goto err_register; |
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} |
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mmc_clock->clk_rate_change_nb.notifier_call = |
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&rockchip_mmc_clk_rate_notify; |
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ret = clk_notifier_register(clk, &mmc_clock->clk_rate_change_nb); |
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if (ret) |
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goto err_notifier; |
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return clk; |
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err_notifier: |
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clk_unregister(clk); |
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err_register: |
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kfree(mmc_clock); |
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return ERR_PTR(ret); |
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}
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