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341 lines
10 KiB
341 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2014 MundoReader S.L. |
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* Author: Heiko Stuebner <[email protected]> |
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* |
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* based on clk/samsung/clk-cpu.c |
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* Copyright (c) 2014 Samsung Electronics Co., Ltd. |
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* Author: Thomas Abraham <[email protected]> |
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* |
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* A CPU clock is defined as a clock supplied to a CPU or a group of CPUs. |
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* The CPU clock is typically derived from a hierarchy of clock |
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* blocks which includes mux and divider blocks. There are a number of other |
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* auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI |
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* clock for CPU domain. The rates of these auxiliary clocks are related to the |
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* CPU clock rate and this relation is usually specified in the hardware manual |
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* of the SoC or supplied after the SoC characterization. |
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* |
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* The below implementation of the CPU clock allows the rate changes of the CPU |
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* clock and the corresponding rate changes of the auxillary clocks of the CPU |
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* domain. The platform clock driver provides a clock register configuration |
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* for each configurable rate which is then used to program the clock hardware |
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* registers to acheive a fast co-oridinated rate change for all the CPU domain |
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* clocks. |
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* |
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* On a rate change request for the CPU clock, the rate change is propagated |
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* upto the PLL supplying the clock to the CPU domain clock blocks. While the |
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* CPU domain PLL is reconfigured, the CPU domain clocks are driven using an |
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* alternate clock source. If required, the alternate clock source is divided |
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* down in order to keep the output clock rate within the previous OPP limits. |
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*/ |
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#include <linux/of.h> |
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#include <linux/slab.h> |
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#include <linux/io.h> |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include "clk.h" |
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/** |
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* struct rockchip_cpuclk: information about clock supplied to a CPU core. |
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* @hw: handle between ccf and cpu clock. |
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* @alt_parent: alternate parent clock to use when switching the speed |
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* of the primary parent clock. |
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* @reg_base: base register for cpu-clock values. |
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* @clk_nb: clock notifier registered for changes in clock speed of the |
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* primary parent clock. |
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* @rate_count: number of rates in the rate_table |
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* @rate_table: pll-rates and their associated dividers |
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* @reg_data: cpu-specific register settings |
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* @lock: clock lock |
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*/ |
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struct rockchip_cpuclk { |
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struct clk_hw hw; |
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struct clk *alt_parent; |
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void __iomem *reg_base; |
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struct notifier_block clk_nb; |
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unsigned int rate_count; |
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struct rockchip_cpuclk_rate_table *rate_table; |
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const struct rockchip_cpuclk_reg_data *reg_data; |
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spinlock_t *lock; |
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}; |
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#define to_rockchip_cpuclk_hw(hw) container_of(hw, struct rockchip_cpuclk, hw) |
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#define to_rockchip_cpuclk_nb(nb) \ |
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container_of(nb, struct rockchip_cpuclk, clk_nb) |
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static const struct rockchip_cpuclk_rate_table *rockchip_get_cpuclk_settings( |
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struct rockchip_cpuclk *cpuclk, unsigned long rate) |
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{ |
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const struct rockchip_cpuclk_rate_table *rate_table = |
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cpuclk->rate_table; |
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int i; |
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for (i = 0; i < cpuclk->rate_count; i++) { |
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if (rate == rate_table[i].prate) |
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return &rate_table[i]; |
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} |
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return NULL; |
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} |
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static unsigned long rockchip_cpuclk_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw); |
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const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; |
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u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg); |
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clksel0 >>= reg_data->div_core_shift; |
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clksel0 &= reg_data->div_core_mask; |
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return parent_rate / (clksel0 + 1); |
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} |
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static const struct clk_ops rockchip_cpuclk_ops = { |
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.recalc_rate = rockchip_cpuclk_recalc_rate, |
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}; |
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static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk, |
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const struct rockchip_cpuclk_rate_table *rate) |
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{ |
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int i; |
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/* alternate parent is active now. set the dividers */ |
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for (i = 0; i < ARRAY_SIZE(rate->divs); i++) { |
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const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i]; |
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if (!clksel->reg) |
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continue; |
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pr_debug("%s: setting reg 0x%x to 0x%x\n", |
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__func__, clksel->reg, clksel->val); |
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writel(clksel->val, cpuclk->reg_base + clksel->reg); |
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} |
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} |
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static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, |
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struct clk_notifier_data *ndata) |
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{ |
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const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; |
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const struct rockchip_cpuclk_rate_table *rate; |
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unsigned long alt_prate, alt_div; |
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unsigned long flags; |
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/* check validity of the new rate */ |
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rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate); |
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if (!rate) { |
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pr_err("%s: Invalid rate : %lu for cpuclk\n", |
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__func__, ndata->new_rate); |
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return -EINVAL; |
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} |
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alt_prate = clk_get_rate(cpuclk->alt_parent); |
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spin_lock_irqsave(cpuclk->lock, flags); |
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/* |
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* If the old parent clock speed is less than the clock speed |
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* of the alternate parent, then it should be ensured that at no point |
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* the armclk speed is more than the old_rate until the dividers are |
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* set. |
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*/ |
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if (alt_prate > ndata->old_rate) { |
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/* calculate dividers */ |
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alt_div = DIV_ROUND_UP(alt_prate, ndata->old_rate) - 1; |
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if (alt_div > reg_data->div_core_mask) { |
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pr_warn("%s: limiting alt-divider %lu to %d\n", |
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__func__, alt_div, reg_data->div_core_mask); |
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alt_div = reg_data->div_core_mask; |
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} |
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/* |
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* Change parents and add dividers in a single transaction. |
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* |
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* NOTE: we do this in a single transaction so we're never |
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* dividing the primary parent by the extra dividers that were |
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* needed for the alt. |
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*/ |
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pr_debug("%s: setting div %lu as alt-rate %lu > old-rate %lu\n", |
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__func__, alt_div, alt_prate, ndata->old_rate); |
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writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask, |
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reg_data->div_core_shift) | |
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HIWORD_UPDATE(reg_data->mux_core_alt, |
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reg_data->mux_core_mask, |
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reg_data->mux_core_shift), |
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cpuclk->reg_base + reg_data->core_reg); |
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} else { |
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/* select alternate parent */ |
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writel(HIWORD_UPDATE(reg_data->mux_core_alt, |
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reg_data->mux_core_mask, |
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reg_data->mux_core_shift), |
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cpuclk->reg_base + reg_data->core_reg); |
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} |
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spin_unlock_irqrestore(cpuclk->lock, flags); |
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return 0; |
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} |
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static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk, |
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struct clk_notifier_data *ndata) |
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{ |
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const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; |
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const struct rockchip_cpuclk_rate_table *rate; |
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unsigned long flags; |
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rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate); |
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if (!rate) { |
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pr_err("%s: Invalid rate : %lu for cpuclk\n", |
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__func__, ndata->new_rate); |
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return -EINVAL; |
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} |
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spin_lock_irqsave(cpuclk->lock, flags); |
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if (ndata->old_rate < ndata->new_rate) |
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rockchip_cpuclk_set_dividers(cpuclk, rate); |
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/* |
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* post-rate change event, re-mux to primary parent and remove dividers. |
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* |
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* NOTE: we do this in a single transaction so we're never dividing the |
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* primary parent by the extra dividers that were needed for the alt. |
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*/ |
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writel(HIWORD_UPDATE(0, reg_data->div_core_mask, |
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reg_data->div_core_shift) | |
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HIWORD_UPDATE(reg_data->mux_core_main, |
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reg_data->mux_core_mask, |
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reg_data->mux_core_shift), |
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cpuclk->reg_base + reg_data->core_reg); |
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if (ndata->old_rate > ndata->new_rate) |
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rockchip_cpuclk_set_dividers(cpuclk, rate); |
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spin_unlock_irqrestore(cpuclk->lock, flags); |
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return 0; |
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} |
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/* |
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* This clock notifier is called when the frequency of the parent clock |
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* of cpuclk is to be changed. This notifier handles the setting up all |
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* the divider clocks, remux to temporary parent and handling the safe |
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* frequency levels when using temporary parent. |
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*/ |
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static int rockchip_cpuclk_notifier_cb(struct notifier_block *nb, |
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unsigned long event, void *data) |
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{ |
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struct clk_notifier_data *ndata = data; |
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struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_nb(nb); |
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int ret = 0; |
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pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n", |
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__func__, event, ndata->old_rate, ndata->new_rate); |
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if (event == PRE_RATE_CHANGE) |
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ret = rockchip_cpuclk_pre_rate_change(cpuclk, ndata); |
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else if (event == POST_RATE_CHANGE) |
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ret = rockchip_cpuclk_post_rate_change(cpuclk, ndata); |
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return notifier_from_errno(ret); |
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} |
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struct clk *rockchip_clk_register_cpuclk(const char *name, |
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const char *const *parent_names, u8 num_parents, |
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const struct rockchip_cpuclk_reg_data *reg_data, |
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const struct rockchip_cpuclk_rate_table *rates, |
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int nrates, void __iomem *reg_base, spinlock_t *lock) |
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{ |
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struct rockchip_cpuclk *cpuclk; |
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struct clk_init_data init; |
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struct clk *clk, *cclk; |
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int ret; |
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if (num_parents < 2) { |
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pr_err("%s: needs at least two parent clocks\n", __func__); |
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return ERR_PTR(-EINVAL); |
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} |
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cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL); |
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if (!cpuclk) |
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return ERR_PTR(-ENOMEM); |
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init.name = name; |
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init.parent_names = &parent_names[reg_data->mux_core_main]; |
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init.num_parents = 1; |
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init.ops = &rockchip_cpuclk_ops; |
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/* only allow rate changes when we have a rate table */ |
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init.flags = (nrates > 0) ? CLK_SET_RATE_PARENT : 0; |
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/* disallow automatic parent changes by ccf */ |
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init.flags |= CLK_SET_RATE_NO_REPARENT; |
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init.flags |= CLK_GET_RATE_NOCACHE; |
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cpuclk->reg_base = reg_base; |
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cpuclk->lock = lock; |
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cpuclk->reg_data = reg_data; |
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cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb; |
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cpuclk->hw.init = &init; |
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cpuclk->alt_parent = __clk_lookup(parent_names[reg_data->mux_core_alt]); |
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if (!cpuclk->alt_parent) { |
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pr_err("%s: could not lookup alternate parent: (%d)\n", |
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__func__, reg_data->mux_core_alt); |
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ret = -EINVAL; |
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goto free_cpuclk; |
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} |
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ret = clk_prepare_enable(cpuclk->alt_parent); |
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if (ret) { |
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pr_err("%s: could not enable alternate parent\n", |
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__func__); |
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goto free_cpuclk; |
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} |
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clk = __clk_lookup(parent_names[reg_data->mux_core_main]); |
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if (!clk) { |
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pr_err("%s: could not lookup parent clock: (%d) %s\n", |
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__func__, reg_data->mux_core_main, |
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parent_names[reg_data->mux_core_main]); |
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ret = -EINVAL; |
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goto free_alt_parent; |
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} |
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ret = clk_notifier_register(clk, &cpuclk->clk_nb); |
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if (ret) { |
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pr_err("%s: failed to register clock notifier for %s\n", |
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__func__, name); |
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goto free_alt_parent; |
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} |
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if (nrates > 0) { |
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cpuclk->rate_count = nrates; |
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cpuclk->rate_table = kmemdup(rates, |
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sizeof(*rates) * nrates, |
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GFP_KERNEL); |
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if (!cpuclk->rate_table) { |
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ret = -ENOMEM; |
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goto unregister_notifier; |
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} |
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} |
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cclk = clk_register(NULL, &cpuclk->hw); |
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if (IS_ERR(cclk)) { |
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pr_err("%s: could not register cpuclk %s\n", __func__, name); |
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ret = PTR_ERR(cclk); |
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goto free_rate_table; |
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} |
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return cclk; |
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free_rate_table: |
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kfree(cpuclk->rate_table); |
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unregister_notifier: |
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clk_notifier_unregister(clk, &cpuclk->clk_nb); |
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free_alt_parent: |
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clk_disable_unprepare(cpuclk->alt_parent); |
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free_cpuclk: |
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kfree(cpuclk); |
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return ERR_PTR(ret); |
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}
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