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123 lines
4.2 KiB
123 lines
4.2 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2017 MediaTek Inc. |
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* Author: Kevin Chen <[email protected]> |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/platform_device.h> |
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#include <dt-bindings/clock/mt6797-clk.h> |
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#include "clk-mtk.h" |
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#include "clk-gate.h" |
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static const struct mtk_gate_regs mm0_cg_regs = { |
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.set_ofs = 0x0104, |
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.clr_ofs = 0x0108, |
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.sta_ofs = 0x0100, |
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}; |
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static const struct mtk_gate_regs mm1_cg_regs = { |
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.set_ofs = 0x0114, |
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.clr_ofs = 0x0118, |
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.sta_ofs = 0x0110, |
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}; |
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#define GATE_MM0(_id, _name, _parent, _shift) { \ |
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.id = _id, \ |
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.name = _name, \ |
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.parent_name = _parent, \ |
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.regs = &mm0_cg_regs, \ |
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.shift = _shift, \ |
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.ops = &mtk_clk_gate_ops_setclr, \ |
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} |
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#define GATE_MM1(_id, _name, _parent, _shift) { \ |
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.id = _id, \ |
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.name = _name, \ |
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.parent_name = _parent, \ |
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.regs = &mm1_cg_regs, \ |
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.shift = _shift, \ |
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.ops = &mtk_clk_gate_ops_setclr, \ |
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} |
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static const struct mtk_gate mm_clks[] = { |
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GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0), |
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GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1), |
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GATE_MM0(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 2), |
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GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 3), |
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GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 4), |
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GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 5), |
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GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 6), |
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GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 7), |
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GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 8), |
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GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 9), |
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GATE_MM0(CLK_MM_MDP_COLOR, "mm_mdp_color", "mm_sel", 10), |
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GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11), |
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GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12), |
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GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13), |
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GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14), |
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GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 15), |
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GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 16), |
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GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 17), |
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GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 18), |
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GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 19), |
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GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 20), |
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GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21), |
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GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22), |
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GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color", "mm_sel", 23), |
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GATE_MM0(CLK_MM_DISP_CCORR, "mm_disp_ccorr", "mm_sel", 24), |
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GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25), |
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GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26), |
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GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 27), |
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GATE_MM0(CLK_MM_DISP_DITHER, "mm_disp_dither", "mm_sel", 28), |
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GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 29), |
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GATE_MM0(CLK_MM_DISP_DSC, "mm_disp_dsc", "mm_sel", 30), |
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GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31), |
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GATE_MM1(CLK_MM_DSI0_MM_CLOCK, "mm_dsi0_mm_clock", "mm_sel", 0), |
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GATE_MM1(CLK_MM_DSI1_MM_CLOCK, "mm_dsi1_mm_clock", "mm_sel", 2), |
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GATE_MM1(CLK_MM_DPI_MM_CLOCK, "mm_dpi_mm_clock", "mm_sel", 4), |
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GATE_MM1(CLK_MM_DPI_INTERFACE_CLOCK, "mm_dpi_interface_clock", |
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"dpi0_sel", 5), |
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GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MM_CLOCK, "mm_larb4_axi_asif_mm_clock", |
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"mm_sel", 6), |
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GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK, "mm_larb4_axi_asif_mjc_clock", |
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"mjc_sel", 7), |
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GATE_MM1(CLK_MM_DISP_OVL0_MOUT_CLOCK, "mm_disp_ovl0_mout_clock", |
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"mm_sel", 8), |
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GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 9), |
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GATE_MM1(CLK_MM_DSI0_INTERFACE_CLOCK, "mm_dsi0_interface_clock", |
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"clk26m", 1), |
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GATE_MM1(CLK_MM_DSI1_INTERFACE_CLOCK, "mm_dsi1_interface_clock", |
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"clk26m", 3), |
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}; |
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static int clk_mt6797_mm_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct device_node *node = dev->parent->of_node; |
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struct clk_onecell_data *clk_data; |
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int r; |
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clk_data = mtk_alloc_clk_data(CLK_MM_NR); |
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mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), |
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clk_data); |
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
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if (r) |
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dev_err(&pdev->dev, |
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"could not register clock provider: %s: %d\n", |
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pdev->name, r); |
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return r; |
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} |
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static struct platform_driver clk_mt6797_mm_drv = { |
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.probe = clk_mt6797_mm_probe, |
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.driver = { |
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.name = "clk-mt6797-mm", |
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}, |
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}; |
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builtin_platform_driver(clk_mt6797_mm_drv);
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