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96 lines
3.1 KiB
96 lines
3.1 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2018 MediaTek Inc. |
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* Author: Owen Chen <[email protected]> |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/platform_device.h> |
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#include "clk-mtk.h" |
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#include "clk-gate.h" |
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#include <dt-bindings/clock/mt6765-clk.h> |
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static const struct mtk_gate_regs mm_cg_regs = { |
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.set_ofs = 0x104, |
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.clr_ofs = 0x108, |
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.sta_ofs = 0x100, |
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}; |
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#define GATE_MM(_id, _name, _parent, _shift) { \ |
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.id = _id, \ |
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.name = _name, \ |
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.parent_name = _parent, \ |
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.regs = &mm_cg_regs, \ |
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.shift = _shift, \ |
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.ops = &mtk_clk_gate_ops_setclr, \ |
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} |
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static const struct mtk_gate mm_clks[] = { |
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/* MM */ |
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GATE_MM(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_ck", 0), |
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GATE_MM(CLK_MM_MDP_CCORR0, "mm_mdp_ccorr0", "mm_ck", 1), |
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GATE_MM(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_ck", 2), |
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GATE_MM(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_ck", 3), |
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GATE_MM(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_ck", 4), |
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GATE_MM(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_ck", 5), |
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GATE_MM(CLK_MM_MDP_WDMA0, "mm_mdp_wdma0", "mm_ck", 6), |
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GATE_MM(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_ck", 7), |
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GATE_MM(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_ck", 8), |
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GATE_MM(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "mm_ck", 9), |
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GATE_MM(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_ck", 10), |
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GATE_MM(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_ck", 11), |
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GATE_MM(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_ck", 12), |
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GATE_MM(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_ck", 13), |
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GATE_MM(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_ck", 14), |
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GATE_MM(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_ck", 15), |
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GATE_MM(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_ck", 16), |
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GATE_MM(CLK_MM_DSI0, "mm_dsi0", "mm_ck", 17), |
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GATE_MM(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_ck", 18), |
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GATE_MM(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_ck", 19), |
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GATE_MM(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_ck", 20), |
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GATE_MM(CLK_MM_SMI_COMM0, "mm_smi_comm0", "mm_ck", 21), |
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GATE_MM(CLK_MM_SMI_COMM1, "mm_smi_comm1", "mm_ck", 22), |
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GATE_MM(CLK_MM_CAM_MDP, "mm_cam_mdp_ck", "mm_ck", 23), |
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GATE_MM(CLK_MM_SMI_IMG, "mm_smi_img_ck", "mm_ck", 24), |
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GATE_MM(CLK_MM_SMI_CAM, "mm_smi_cam_ck", "mm_ck", 25), |
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GATE_MM(CLK_MM_IMG_DL_RELAY, "mm_img_dl_relay", "mm_ck", 26), |
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GATE_MM(CLK_MM_IMG_DL_ASYNC_TOP, "mm_imgdl_async", "mm_ck", 27), |
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GATE_MM(CLK_MM_DIG_DSI, "mm_dig_dsi_ck", "mm_ck", 28), |
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GATE_MM(CLK_MM_F26M_HRTWT, "mm_hrtwt", "f_f26m_ck", 29), |
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}; |
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static int clk_mt6765_mm_probe(struct platform_device *pdev) |
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{ |
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struct clk_onecell_data *clk_data; |
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int r; |
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struct device_node *node = pdev->dev.of_node; |
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clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); |
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mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), clk_data); |
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
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if (r) |
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pr_err("%s(): could not register clock provider: %d\n", |
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__func__, r); |
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return r; |
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} |
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static const struct of_device_id of_match_clk_mt6765_mm[] = { |
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{ .compatible = "mediatek,mt6765-mmsys", }, |
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{} |
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}; |
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static struct platform_driver clk_mt6765_mm_drv = { |
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.probe = clk_mt6765_mm_probe, |
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.driver = { |
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.name = "clk-mt6765-mm", |
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.of_match_table = of_match_clk_mt6765_mm, |
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}, |
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}; |
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builtin_platform_driver(clk_mt6765_mm_drv);
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