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461 lines
11 KiB
461 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* X1830 SoC CGU driver |
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* Copyright (c) 2019 周琰杰 (Zhou Yanjie) <[email protected]> |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <dt-bindings/clock/x1830-cgu.h> |
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#include "cgu.h" |
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#include "pm.h" |
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/* CGU register offsets */ |
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#define CGU_REG_CPCCR 0x00 |
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#define CGU_REG_CPPCR 0x0c |
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#define CGU_REG_APLL 0x10 |
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#define CGU_REG_MPLL 0x14 |
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#define CGU_REG_CLKGR0 0x20 |
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#define CGU_REG_OPCR 0x24 |
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#define CGU_REG_CLKGR1 0x28 |
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#define CGU_REG_DDRCDR 0x2c |
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#define CGU_REG_USBPCR 0x3c |
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#define CGU_REG_USBRDT 0x40 |
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#define CGU_REG_USBVBFIL 0x44 |
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#define CGU_REG_USBPCR1 0x48 |
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#define CGU_REG_MACCDR 0x54 |
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#define CGU_REG_EPLL 0x58 |
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#define CGU_REG_I2SCDR 0x60 |
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#define CGU_REG_LPCDR 0x64 |
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#define CGU_REG_MSC0CDR 0x68 |
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#define CGU_REG_I2SCDR1 0x70 |
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#define CGU_REG_SSICDR 0x74 |
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#define CGU_REG_CIMCDR 0x7c |
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#define CGU_REG_MSC1CDR 0xa4 |
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#define CGU_REG_CMP_INTR 0xb0 |
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#define CGU_REG_CMP_INTRE 0xb4 |
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#define CGU_REG_DRCG 0xd0 |
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#define CGU_REG_CPCSR 0xd4 |
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#define CGU_REG_VPLL 0xe0 |
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#define CGU_REG_MACPHYC 0xe8 |
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/* bits within the OPCR register */ |
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#define OPCR_GATE_USBPHYCLK BIT(23) |
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#define OPCR_SPENDN0 BIT(7) |
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#define OPCR_SPENDN1 BIT(6) |
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/* bits within the USBPCR register */ |
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#define USBPCR_SIDDQ BIT(21) |
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#define USBPCR_OTG_DISABLE BIT(20) |
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static struct ingenic_cgu *cgu; |
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static int x1830_usb_phy_enable(struct clk_hw *hw) |
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{ |
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void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; |
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void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; |
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writel((readl(reg_opcr) | OPCR_SPENDN0) & ~OPCR_GATE_USBPHYCLK, reg_opcr); |
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writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr); |
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return 0; |
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} |
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static void x1830_usb_phy_disable(struct clk_hw *hw) |
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{ |
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void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; |
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void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; |
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writel((readl(reg_opcr) & ~OPCR_SPENDN0) | OPCR_GATE_USBPHYCLK, reg_opcr); |
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writel(readl(reg_usbpcr) | USBPCR_OTG_DISABLE | USBPCR_SIDDQ, reg_usbpcr); |
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} |
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static int x1830_usb_phy_is_enabled(struct clk_hw *hw) |
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{ |
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void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; |
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void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; |
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return (readl(reg_opcr) & OPCR_SPENDN0) && |
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!(readl(reg_usbpcr) & USBPCR_SIDDQ) && |
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!(readl(reg_usbpcr) & USBPCR_OTG_DISABLE); |
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} |
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static const struct clk_ops x1830_otg_phy_ops = { |
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.enable = x1830_usb_phy_enable, |
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.disable = x1830_usb_phy_disable, |
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.is_enabled = x1830_usb_phy_is_enabled, |
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}; |
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static const s8 pll_od_encoding[64] = { |
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0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3, |
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-1, -1, -1, -1, -1, -1, -1, 0x4, |
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-1, -1, -1, -1, -1, -1, -1, -1, |
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-1, -1, -1, -1, -1, -1, -1, 0x5, |
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-1, -1, -1, -1, -1, -1, -1, -1, |
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-1, -1, -1, -1, -1, -1, -1, -1, |
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-1, -1, -1, -1, -1, -1, -1, -1, |
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-1, -1, -1, -1, -1, -1, -1, 0x6, |
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}; |
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static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { |
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/* External clocks */ |
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[X1830_CLK_EXCLK] = { "ext", CGU_CLK_EXT }, |
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[X1830_CLK_RTCLK] = { "rtc", CGU_CLK_EXT }, |
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/* PLLs */ |
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[X1830_CLK_APLL] = { |
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"apll", CGU_CLK_PLL, |
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.parents = { X1830_CLK_EXCLK, -1, -1, -1 }, |
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.pll = { |
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.reg = CGU_REG_APLL, |
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.rate_multiplier = 2, |
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.m_shift = 20, |
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.m_bits = 9, |
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.m_offset = 1, |
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.n_shift = 14, |
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.n_bits = 6, |
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.n_offset = 1, |
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.od_shift = 11, |
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.od_bits = 3, |
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.od_max = 64, |
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.od_encoding = pll_od_encoding, |
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.bypass_reg = CGU_REG_CPPCR, |
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.bypass_bit = 30, |
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.enable_bit = 0, |
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.stable_bit = 3, |
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}, |
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}, |
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[X1830_CLK_MPLL] = { |
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"mpll", CGU_CLK_PLL, |
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.parents = { X1830_CLK_EXCLK, -1, -1, -1 }, |
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.pll = { |
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.reg = CGU_REG_MPLL, |
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.rate_multiplier = 2, |
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.m_shift = 20, |
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.m_bits = 9, |
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.m_offset = 1, |
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.n_shift = 14, |
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.n_bits = 6, |
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.n_offset = 1, |
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.od_shift = 11, |
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.od_bits = 3, |
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.od_max = 64, |
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.od_encoding = pll_od_encoding, |
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.bypass_reg = CGU_REG_CPPCR, |
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.bypass_bit = 28, |
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.enable_bit = 0, |
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.stable_bit = 3, |
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}, |
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}, |
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[X1830_CLK_EPLL] = { |
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"epll", CGU_CLK_PLL, |
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.parents = { X1830_CLK_EXCLK, -1, -1, -1 }, |
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.pll = { |
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.reg = CGU_REG_EPLL, |
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.rate_multiplier = 2, |
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.m_shift = 20, |
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.m_bits = 9, |
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.m_offset = 1, |
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.n_shift = 14, |
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.n_bits = 6, |
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.n_offset = 1, |
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.od_shift = 11, |
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.od_bits = 3, |
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.od_max = 64, |
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.od_encoding = pll_od_encoding, |
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.bypass_reg = CGU_REG_CPPCR, |
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.bypass_bit = 24, |
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.enable_bit = 0, |
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.stable_bit = 3, |
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}, |
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}, |
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[X1830_CLK_VPLL] = { |
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"vpll", CGU_CLK_PLL, |
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.parents = { X1830_CLK_EXCLK, -1, -1, -1 }, |
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.pll = { |
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.reg = CGU_REG_VPLL, |
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.rate_multiplier = 2, |
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.m_shift = 20, |
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.m_bits = 9, |
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.m_offset = 1, |
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.n_shift = 14, |
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.n_bits = 6, |
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.n_offset = 1, |
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.od_shift = 11, |
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.od_bits = 3, |
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.od_max = 64, |
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.od_encoding = pll_od_encoding, |
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.bypass_reg = CGU_REG_CPPCR, |
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.bypass_bit = 26, |
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.enable_bit = 0, |
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.stable_bit = 3, |
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}, |
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}, |
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/* Custom (SoC-specific) OTG PHY */ |
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[X1830_CLK_OTGPHY] = { |
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"otg_phy", CGU_CLK_CUSTOM, |
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.parents = { X1830_CLK_EXCLK, -1, -1, -1 }, |
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.custom = { &x1830_otg_phy_ops }, |
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}, |
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/* Muxes & dividers */ |
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[X1830_CLK_SCLKA] = { |
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"sclk_a", CGU_CLK_MUX, |
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.parents = { -1, X1830_CLK_EXCLK, X1830_CLK_APLL, -1 }, |
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.mux = { CGU_REG_CPCCR, 30, 2 }, |
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}, |
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[X1830_CLK_CPUMUX] = { |
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"cpu_mux", CGU_CLK_MUX, |
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.parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, |
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.mux = { CGU_REG_CPCCR, 28, 2 }, |
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}, |
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[X1830_CLK_CPU] = { |
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"cpu", CGU_CLK_DIV | CGU_CLK_GATE, |
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.parents = { X1830_CLK_CPUMUX, -1, -1, -1 }, |
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.div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 }, |
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.gate = { CGU_REG_CLKGR1, 15 }, |
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}, |
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[X1830_CLK_L2CACHE] = { |
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"l2cache", CGU_CLK_DIV, |
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.parents = { X1830_CLK_CPUMUX, -1, -1, -1 }, |
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.div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 }, |
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}, |
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[X1830_CLK_AHB0] = { |
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"ahb0", CGU_CLK_MUX | CGU_CLK_DIV, |
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.parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, |
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.mux = { CGU_REG_CPCCR, 26, 2 }, |
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.div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 }, |
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}, |
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[X1830_CLK_AHB2PMUX] = { |
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"ahb2_apb_mux", CGU_CLK_MUX, |
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.parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, |
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.mux = { CGU_REG_CPCCR, 24, 2 }, |
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}, |
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[X1830_CLK_AHB2] = { |
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"ahb2", CGU_CLK_DIV, |
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.parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 }, |
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.div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 }, |
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}, |
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[X1830_CLK_PCLK] = { |
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"pclk", CGU_CLK_DIV | CGU_CLK_GATE, |
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.parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 }, |
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.div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 }, |
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.gate = { CGU_REG_CLKGR1, 14 }, |
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}, |
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[X1830_CLK_DDR] = { |
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"ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, |
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.parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, |
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.mux = { CGU_REG_DDRCDR, 30, 2 }, |
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.div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 }, |
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.gate = { CGU_REG_CLKGR0, 31 }, |
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}, |
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[X1830_CLK_MAC] = { |
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"mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, |
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.parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, |
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X1830_CLK_VPLL, X1830_CLK_EPLL }, |
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.mux = { CGU_REG_MACCDR, 30, 2 }, |
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.div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 }, |
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.gate = { CGU_REG_CLKGR1, 4 }, |
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}, |
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[X1830_CLK_LCD] = { |
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"lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, |
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.parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, |
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X1830_CLK_VPLL, X1830_CLK_EPLL }, |
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.mux = { CGU_REG_LPCDR, 30, 2 }, |
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.div = { CGU_REG_LPCDR, 0, 1, 8, 28, 27, 26 }, |
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.gate = { CGU_REG_CLKGR1, 9 }, |
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}, |
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[X1830_CLK_MSCMUX] = { |
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"msc_mux", CGU_CLK_MUX, |
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.parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, |
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X1830_CLK_VPLL, X1830_CLK_EPLL }, |
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.mux = { CGU_REG_MSC0CDR, 30, 2 }, |
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}, |
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[X1830_CLK_MSC0] = { |
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"msc0", CGU_CLK_DIV | CGU_CLK_GATE, |
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.parents = { X1830_CLK_MSCMUX, -1, -1, -1 }, |
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.div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 }, |
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.gate = { CGU_REG_CLKGR0, 4 }, |
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}, |
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[X1830_CLK_MSC1] = { |
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"msc1", CGU_CLK_DIV | CGU_CLK_GATE, |
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.parents = { X1830_CLK_MSCMUX, -1, -1, -1 }, |
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.div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 }, |
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.gate = { CGU_REG_CLKGR0, 5 }, |
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}, |
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[X1830_CLK_SSIPLL] = { |
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"ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV, |
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.parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, |
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X1830_CLK_VPLL, X1830_CLK_EPLL }, |
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.mux = { CGU_REG_SSICDR, 30, 2 }, |
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.div = { CGU_REG_SSICDR, 0, 1, 8, 28, 27, 26 }, |
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}, |
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[X1830_CLK_SSIPLL_DIV2] = { |
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"ssi_pll_div2", CGU_CLK_FIXDIV, |
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.parents = { X1830_CLK_SSIPLL }, |
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.fixdiv = { 2 }, |
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}, |
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[X1830_CLK_SSIMUX] = { |
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"ssi_mux", CGU_CLK_MUX, |
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.parents = { X1830_CLK_EXCLK, X1830_CLK_SSIPLL_DIV2, -1, -1 }, |
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.mux = { CGU_REG_SSICDR, 29, 1 }, |
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}, |
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[X1830_CLK_EXCLK_DIV512] = { |
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"exclk_div512", CGU_CLK_FIXDIV, |
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.parents = { X1830_CLK_EXCLK }, |
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.fixdiv = { 512 }, |
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}, |
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[X1830_CLK_RTC] = { |
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"rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE, |
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.parents = { X1830_CLK_EXCLK_DIV512, X1830_CLK_RTCLK }, |
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.mux = { CGU_REG_OPCR, 2, 1}, |
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.gate = { CGU_REG_CLKGR0, 29 }, |
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}, |
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/* Gate-only clocks */ |
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[X1830_CLK_EMC] = { |
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"emc", CGU_CLK_GATE, |
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.parents = { X1830_CLK_AHB2, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR0, 0 }, |
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}, |
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[X1830_CLK_EFUSE] = { |
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"efuse", CGU_CLK_GATE, |
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.parents = { X1830_CLK_AHB2, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR0, 1 }, |
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}, |
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[X1830_CLK_OTG] = { |
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"otg", CGU_CLK_GATE, |
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.parents = { X1830_CLK_EXCLK, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR0, 3 }, |
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}, |
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[X1830_CLK_SSI0] = { |
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"ssi0", CGU_CLK_GATE, |
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.parents = { X1830_CLK_SSIMUX, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR0, 6 }, |
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}, |
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[X1830_CLK_SMB0] = { |
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"smb0", CGU_CLK_GATE, |
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.parents = { X1830_CLK_PCLK, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR0, 7 }, |
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}, |
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[X1830_CLK_SMB1] = { |
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"smb1", CGU_CLK_GATE, |
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.parents = { X1830_CLK_PCLK, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR0, 8 }, |
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}, |
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[X1830_CLK_SMB2] = { |
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"smb2", CGU_CLK_GATE, |
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.parents = { X1830_CLK_PCLK, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR0, 9 }, |
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}, |
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[X1830_CLK_UART0] = { |
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"uart0", CGU_CLK_GATE, |
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.parents = { X1830_CLK_EXCLK, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR0, 14 }, |
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}, |
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[X1830_CLK_UART1] = { |
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"uart1", CGU_CLK_GATE, |
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.parents = { X1830_CLK_EXCLK, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR0, 15 }, |
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}, |
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[X1830_CLK_SSI1] = { |
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"ssi1", CGU_CLK_GATE, |
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.parents = { X1830_CLK_SSIMUX, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR0, 19 }, |
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}, |
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[X1830_CLK_SFC] = { |
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"sfc", CGU_CLK_GATE, |
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.parents = { X1830_CLK_SSIPLL, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR0, 20 }, |
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}, |
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[X1830_CLK_PDMA] = { |
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"pdma", CGU_CLK_GATE, |
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.parents = { X1830_CLK_EXCLK, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR0, 21 }, |
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}, |
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[X1830_CLK_TCU] = { |
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"tcu", CGU_CLK_GATE, |
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.parents = { X1830_CLK_EXCLK, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR0, 30 }, |
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}, |
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[X1830_CLK_DTRNG] = { |
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"dtrng", CGU_CLK_GATE, |
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.parents = { X1830_CLK_PCLK, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR1, 1 }, |
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}, |
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[X1830_CLK_OST] = { |
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"ost", CGU_CLK_GATE, |
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.parents = { X1830_CLK_EXCLK, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR1, 11 }, |
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}, |
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}; |
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static void __init x1830_cgu_init(struct device_node *np) |
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{ |
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int retval; |
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cgu = ingenic_cgu_new(x1830_cgu_clocks, |
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ARRAY_SIZE(x1830_cgu_clocks), np); |
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if (!cgu) { |
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pr_err("%s: failed to initialise CGU\n", __func__); |
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return; |
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} |
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retval = ingenic_cgu_register_clocks(cgu); |
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if (retval) { |
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pr_err("%s: failed to register CGU Clocks\n", __func__); |
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return; |
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} |
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ingenic_cgu_register_syscore_ops(cgu); |
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} |
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/* |
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* CGU has some children devices, this is useful for probing children devices |
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* in the case where the device node is compatible with "simple-mfd". |
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*/ |
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CLK_OF_DECLARE_DRIVER(x1830_cgu, "ingenic,x1830-cgu", x1830_cgu_init);
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