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360 lines
9.7 KiB
360 lines
9.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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#include <linux/clk-provider.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/slab.h> |
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#include <dt-bindings/clock/at91.h> |
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#include "pmc.h" |
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static DEFINE_SPINLOCK(pmc_pll_lock); |
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static DEFINE_SPINLOCK(mck_lock); |
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static const struct clk_master_characteristics mck_characteristics = { |
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.output = { .min = 140000000, .max = 200000000 }, |
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.divisors = { 1, 2, 4, 3 }, |
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.have_div3_pres = 1, |
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}; |
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static const struct clk_master_layout sam9x60_master_layout = { |
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.mask = 0x373, |
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.pres_shift = 4, |
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.offset = 0x28, |
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}; |
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static const struct clk_range plla_outputs[] = { |
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{ .min = 2343750, .max = 1200000000 }, |
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}; |
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static const struct clk_pll_characteristics plla_characteristics = { |
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.input = { .min = 12000000, .max = 48000000 }, |
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.num_output = ARRAY_SIZE(plla_outputs), |
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.output = plla_outputs, |
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}; |
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static const struct clk_range upll_outputs[] = { |
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{ .min = 300000000, .max = 500000000 }, |
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}; |
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static const struct clk_pll_characteristics upll_characteristics = { |
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.input = { .min = 12000000, .max = 48000000 }, |
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.num_output = ARRAY_SIZE(upll_outputs), |
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.output = upll_outputs, |
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.upll = true, |
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}; |
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static const struct clk_pll_layout pll_frac_layout = { |
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.mul_mask = GENMASK(31, 24), |
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.frac_mask = GENMASK(21, 0), |
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.mul_shift = 24, |
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.frac_shift = 0, |
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}; |
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static const struct clk_pll_layout pll_div_layout = { |
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.div_mask = GENMASK(7, 0), |
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.endiv_mask = BIT(29), |
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.div_shift = 0, |
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.endiv_shift = 29, |
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}; |
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static const struct clk_programmable_layout sam9x60_programmable_layout = { |
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.pres_mask = 0xff, |
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.pres_shift = 8, |
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.css_mask = 0x1f, |
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.have_slck_mck = 0, |
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.is_pres_direct = 1, |
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}; |
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static const struct clk_pcr_layout sam9x60_pcr_layout = { |
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.offset = 0x88, |
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.cmd = BIT(31), |
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.gckcss_mask = GENMASK(12, 8), |
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.pid_mask = GENMASK(6, 0), |
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}; |
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static const struct { |
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char *n; |
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char *p; |
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u8 id; |
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} sam9x60_systemck[] = { |
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{ .n = "ddrck", .p = "masterck_div", .id = 2 }, |
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{ .n = "uhpck", .p = "usbck", .id = 6 }, |
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{ .n = "pck0", .p = "prog0", .id = 8 }, |
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{ .n = "pck1", .p = "prog1", .id = 9 }, |
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{ .n = "qspick", .p = "masterck_div", .id = 19 }, |
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}; |
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static const struct { |
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char *n; |
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u8 id; |
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} sam9x60_periphck[] = { |
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{ .n = "pioA_clk", .id = 2, }, |
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{ .n = "pioB_clk", .id = 3, }, |
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{ .n = "pioC_clk", .id = 4, }, |
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{ .n = "flex0_clk", .id = 5, }, |
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{ .n = "flex1_clk", .id = 6, }, |
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{ .n = "flex2_clk", .id = 7, }, |
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{ .n = "flex3_clk", .id = 8, }, |
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{ .n = "flex6_clk", .id = 9, }, |
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{ .n = "flex7_clk", .id = 10, }, |
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{ .n = "flex8_clk", .id = 11, }, |
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{ .n = "sdmmc0_clk", .id = 12, }, |
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{ .n = "flex4_clk", .id = 13, }, |
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{ .n = "flex5_clk", .id = 14, }, |
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{ .n = "flex9_clk", .id = 15, }, |
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{ .n = "flex10_clk", .id = 16, }, |
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{ .n = "tcb0_clk", .id = 17, }, |
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{ .n = "pwm_clk", .id = 18, }, |
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{ .n = "adc_clk", .id = 19, }, |
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{ .n = "dma0_clk", .id = 20, }, |
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{ .n = "matrix_clk", .id = 21, }, |
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{ .n = "uhphs_clk", .id = 22, }, |
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{ .n = "udphs_clk", .id = 23, }, |
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{ .n = "macb0_clk", .id = 24, }, |
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{ .n = "lcd_clk", .id = 25, }, |
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{ .n = "sdmmc1_clk", .id = 26, }, |
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{ .n = "macb1_clk", .id = 27, }, |
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{ .n = "ssc_clk", .id = 28, }, |
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{ .n = "can0_clk", .id = 29, }, |
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{ .n = "can1_clk", .id = 30, }, |
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{ .n = "flex11_clk", .id = 32, }, |
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{ .n = "flex12_clk", .id = 33, }, |
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{ .n = "i2s_clk", .id = 34, }, |
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{ .n = "qspi_clk", .id = 35, }, |
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{ .n = "gfx2d_clk", .id = 36, }, |
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{ .n = "pit64b_clk", .id = 37, }, |
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{ .n = "trng_clk", .id = 38, }, |
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{ .n = "aes_clk", .id = 39, }, |
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{ .n = "tdes_clk", .id = 40, }, |
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{ .n = "sha_clk", .id = 41, }, |
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{ .n = "classd_clk", .id = 42, }, |
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{ .n = "isi_clk", .id = 43, }, |
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{ .n = "pioD_clk", .id = 44, }, |
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{ .n = "tcb1_clk", .id = 45, }, |
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{ .n = "dbgu_clk", .id = 47, }, |
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{ .n = "mpddr_clk", .id = 49, }, |
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}; |
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static const struct { |
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char *n; |
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u8 id; |
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struct clk_range r; |
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} sam9x60_gck[] = { |
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{ .n = "flex0_gclk", .id = 5, }, |
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{ .n = "flex1_gclk", .id = 6, }, |
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{ .n = "flex2_gclk", .id = 7, }, |
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{ .n = "flex3_gclk", .id = 8, }, |
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{ .n = "flex6_gclk", .id = 9, }, |
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{ .n = "flex7_gclk", .id = 10, }, |
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{ .n = "flex8_gclk", .id = 11, }, |
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{ .n = "sdmmc0_gclk", .id = 12, .r = { .min = 0, .max = 105000000 }, }, |
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{ .n = "flex4_gclk", .id = 13, }, |
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{ .n = "flex5_gclk", .id = 14, }, |
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{ .n = "flex9_gclk", .id = 15, }, |
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{ .n = "flex10_gclk", .id = 16, }, |
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{ .n = "tcb0_gclk", .id = 17, }, |
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{ .n = "adc_gclk", .id = 19, }, |
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{ .n = "lcd_gclk", .id = 25, .r = { .min = 0, .max = 140000000 }, }, |
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{ .n = "sdmmc1_gclk", .id = 26, .r = { .min = 0, .max = 105000000 }, }, |
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{ .n = "flex11_gclk", .id = 32, }, |
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{ .n = "flex12_gclk", .id = 33, }, |
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{ .n = "i2s_gclk", .id = 34, .r = { .min = 0, .max = 105000000 }, }, |
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{ .n = "pit64b_gclk", .id = 37, }, |
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{ .n = "classd_gclk", .id = 42, .r = { .min = 0, .max = 100000000 }, }, |
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{ .n = "tcb1_gclk", .id = 45, }, |
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{ .n = "dbgu_gclk", .id = 47, }, |
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}; |
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static void __init sam9x60_pmc_setup(struct device_node *np) |
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{ |
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struct clk_range range = CLK_RANGE(0, 0); |
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const char *td_slck_name, *md_slck_name, *mainxtal_name; |
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struct pmc_data *sam9x60_pmc; |
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const char *parent_names[6]; |
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struct clk_hw *main_osc_hw; |
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struct regmap *regmap; |
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struct clk_hw *hw; |
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int i; |
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i = of_property_match_string(np, "clock-names", "td_slck"); |
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if (i < 0) |
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return; |
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td_slck_name = of_clk_get_parent_name(np, i); |
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i = of_property_match_string(np, "clock-names", "md_slck"); |
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if (i < 0) |
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return; |
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md_slck_name = of_clk_get_parent_name(np, i); |
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i = of_property_match_string(np, "clock-names", "main_xtal"); |
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if (i < 0) |
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return; |
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mainxtal_name = of_clk_get_parent_name(np, i); |
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regmap = device_node_to_regmap(np); |
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if (IS_ERR(regmap)) |
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return; |
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sam9x60_pmc = pmc_data_allocate(PMC_PLLACK + 1, |
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nck(sam9x60_systemck), |
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nck(sam9x60_periphck), |
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nck(sam9x60_gck), 8); |
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if (!sam9x60_pmc) |
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return; |
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hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, |
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50000000); |
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if (IS_ERR(hw)) |
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goto err_free; |
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hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, 0); |
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if (IS_ERR(hw)) |
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goto err_free; |
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main_osc_hw = hw; |
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parent_names[0] = "main_rc_osc"; |
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parent_names[1] = "main_osc"; |
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hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2); |
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if (IS_ERR(hw)) |
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goto err_free; |
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sam9x60_pmc->chws[PMC_MAIN] = hw; |
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hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracck", |
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"mainck", sam9x60_pmc->chws[PMC_MAIN], |
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0, &plla_characteristics, |
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&pll_frac_layout, |
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/* |
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* This feeds pllack_divck which |
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* feeds CPU. It should not be |
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* disabled. |
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*/ |
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CLK_IS_CRITICAL | CLK_SET_RATE_GATE); |
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if (IS_ERR(hw)) |
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goto err_free; |
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hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "pllack_divck", |
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"pllack_fracck", 0, &plla_characteristics, |
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&pll_div_layout, |
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/* |
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* This feeds CPU. It should not |
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* be disabled. |
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*/ |
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CLK_IS_CRITICAL | CLK_SET_RATE_GATE); |
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if (IS_ERR(hw)) |
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goto err_free; |
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sam9x60_pmc->chws[PMC_PLLACK] = hw; |
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hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracck", |
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"main_osc", main_osc_hw, 1, |
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&upll_characteristics, |
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&pll_frac_layout, CLK_SET_RATE_GATE); |
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if (IS_ERR(hw)) |
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goto err_free; |
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hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "upllck_divck", |
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"upllck_fracck", 1, &upll_characteristics, |
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&pll_div_layout, |
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CLK_SET_RATE_GATE | |
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CLK_SET_PARENT_GATE | |
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CLK_SET_RATE_PARENT); |
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if (IS_ERR(hw)) |
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goto err_free; |
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sam9x60_pmc->chws[PMC_UTMI] = hw; |
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parent_names[0] = md_slck_name; |
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parent_names[1] = "mainck"; |
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parent_names[2] = "pllack_divck"; |
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hw = at91_clk_register_master_pres(regmap, "masterck_pres", 3, |
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parent_names, &sam9x60_master_layout, |
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&mck_characteristics, &mck_lock, |
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CLK_SET_RATE_GATE, INT_MIN); |
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if (IS_ERR(hw)) |
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goto err_free; |
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hw = at91_clk_register_master_div(regmap, "masterck_div", |
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"masterck_pres", &sam9x60_master_layout, |
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&mck_characteristics, &mck_lock, |
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CLK_SET_RATE_GATE); |
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if (IS_ERR(hw)) |
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goto err_free; |
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sam9x60_pmc->chws[PMC_MCK] = hw; |
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parent_names[0] = "pllack_divck"; |
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parent_names[1] = "upllck_divck"; |
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parent_names[2] = "main_osc"; |
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hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); |
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if (IS_ERR(hw)) |
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goto err_free; |
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parent_names[0] = md_slck_name; |
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parent_names[1] = td_slck_name; |
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parent_names[2] = "mainck"; |
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parent_names[3] = "masterck_div"; |
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parent_names[4] = "pllack_divck"; |
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parent_names[5] = "upllck_divck"; |
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for (i = 0; i < 2; i++) { |
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char name[6]; |
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snprintf(name, sizeof(name), "prog%d", i); |
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hw = at91_clk_register_programmable(regmap, name, |
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parent_names, 6, i, |
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&sam9x60_programmable_layout, |
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NULL); |
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if (IS_ERR(hw)) |
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goto err_free; |
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sam9x60_pmc->pchws[i] = hw; |
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} |
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for (i = 0; i < ARRAY_SIZE(sam9x60_systemck); i++) { |
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hw = at91_clk_register_system(regmap, sam9x60_systemck[i].n, |
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sam9x60_systemck[i].p, |
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sam9x60_systemck[i].id); |
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if (IS_ERR(hw)) |
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goto err_free; |
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sam9x60_pmc->shws[sam9x60_systemck[i].id] = hw; |
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} |
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for (i = 0; i < ARRAY_SIZE(sam9x60_periphck); i++) { |
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hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, |
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&sam9x60_pcr_layout, |
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sam9x60_periphck[i].n, |
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"masterck_div", |
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sam9x60_periphck[i].id, |
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&range, INT_MIN); |
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if (IS_ERR(hw)) |
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goto err_free; |
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sam9x60_pmc->phws[sam9x60_periphck[i].id] = hw; |
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} |
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for (i = 0; i < ARRAY_SIZE(sam9x60_gck); i++) { |
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hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, |
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&sam9x60_pcr_layout, |
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sam9x60_gck[i].n, |
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parent_names, NULL, 6, |
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sam9x60_gck[i].id, |
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&sam9x60_gck[i].r, INT_MIN); |
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if (IS_ERR(hw)) |
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goto err_free; |
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sam9x60_pmc->ghws[sam9x60_gck[i].id] = hw; |
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} |
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of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x60_pmc); |
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return; |
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err_free: |
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kfree(sam9x60_pmc); |
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} |
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/* Some clks are used for a clocksource */ |
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CLK_OF_DECLARE(sam9x60_pmc, "microchip,sam9x60-pmc", sam9x60_pmc_setup);
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