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501 lines
12 KiB
501 lines
12 KiB
/* |
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* OMAP L3 Interconnect error handling driver header |
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* |
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* Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/ |
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* Santosh Shilimkar <[email protected]> |
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* sricharan <[email protected]> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any |
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* kind, whether express or implied; without even the implied warranty |
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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#ifndef __OMAP_L3_NOC_H |
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#define __OMAP_L3_NOC_H |
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#define MAX_L3_MODULES 3 |
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#define MAX_CLKDM_TARGETS 31 |
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|
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#define CLEAR_STDERR_LOG (1 << 31) |
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#define CUSTOM_ERROR 0x2 |
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#define STANDARD_ERROR 0x0 |
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#define INBAND_ERROR 0x0 |
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#define L3_APPLICATION_ERROR 0x0 |
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#define L3_DEBUG_ERROR 0x1 |
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|
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/* L3 TARG register offsets */ |
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#define L3_TARG_STDERRLOG_MAIN 0x48 |
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#define L3_TARG_STDERRLOG_HDR 0x4c |
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#define L3_TARG_STDERRLOG_MSTADDR 0x50 |
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#define L3_TARG_STDERRLOG_INFO 0x58 |
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#define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c |
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#define L3_TARG_STDERRLOG_CINFO_INFO 0x64 |
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#define L3_TARG_STDERRLOG_CINFO_MSTADDR 0x68 |
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#define L3_TARG_STDERRLOG_CINFO_OPCODE 0x6c |
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#define L3_FLAGMUX_REGERR0 0xc |
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#define L3_FLAGMUX_MASK0 0x8 |
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#define L3_TARGET_NOT_SUPPORTED NULL |
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#define L3_BASE_IS_SUBMODULE ((void __iomem *)(1 << 0)) |
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static const char * const l3_transaction_type[] = { |
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/* 0 0 0 */ "Idle", |
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/* 0 0 1 */ "Write", |
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/* 0 1 0 */ "Read", |
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/* 0 1 1 */ "ReadEx", |
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/* 1 0 0 */ "Read Link", |
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/* 1 0 1 */ "Write Non-Posted", |
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/* 1 1 0 */ "Write Conditional", |
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/* 1 1 1 */ "Write Broadcast", |
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}; |
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/** |
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* struct l3_masters_data - L3 Master information |
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* @id: ID of the L3 Master |
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* @name: master name |
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*/ |
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struct l3_masters_data { |
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u32 id; |
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char *name; |
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}; |
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/** |
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* struct l3_target_data - L3 Target information |
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* @offset: Offset from base for L3 Target |
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* @name: Target name |
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* |
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* Target information is organized indexed by bit field definitions. |
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*/ |
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struct l3_target_data { |
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u32 offset; |
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char *name; |
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}; |
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/** |
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* struct l3_flagmux_data - Flag Mux information |
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* @offset: offset from base for flagmux register |
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* @l3_targ: array indexed by flagmux index (bit offset) pointing to the |
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* target data. unsupported ones are marked with |
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* L3_TARGET_NOT_SUPPORTED |
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* @num_targ_data: number of entries in target data |
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* @mask_app_bits: ignore these from raw application irq status |
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* @mask_dbg_bits: ignore these from raw debug irq status |
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*/ |
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struct l3_flagmux_data { |
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u32 offset; |
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struct l3_target_data *l3_targ; |
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u8 num_targ_data; |
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u32 mask_app_bits; |
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u32 mask_dbg_bits; |
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}; |
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/** |
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* struct omap_l3 - Description of data relevant for L3 bus. |
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* @dev: device representing the bus (populated runtime) |
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* @l3_base: base addresses of modules (populated runtime if 0) |
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* if set to L3_BASE_IS_SUBMODULE, then uses previous |
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* module index as the base address |
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* @l3_flag_mux: array containing flag mux data per module |
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* offset from corresponding module base indexed per |
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* module. |
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* @num_modules: number of clock domains / modules. |
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* @l3_masters: array pointing to master data containing name and register |
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* offset for the master. |
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* @num_master: number of masters |
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* @mst_addr_mask: Mask representing MSTADDR information of NTTP packet |
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* @debug_irq: irq number of the debug interrupt (populated runtime) |
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* @app_irq: irq number of the application interrupt (populated runtime) |
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*/ |
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struct omap_l3 { |
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struct device *dev; |
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void __iomem *l3_base[MAX_L3_MODULES]; |
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struct l3_flagmux_data **l3_flagmux; |
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int num_modules; |
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struct l3_masters_data *l3_masters; |
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int num_masters; |
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u32 mst_addr_mask; |
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int debug_irq; |
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int app_irq; |
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}; |
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static struct l3_target_data omap_l3_target_data_clk1[] = { |
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{0x100, "DMM1",}, |
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{0x200, "DMM2",}, |
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{0x300, "ABE",}, |
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{0x400, "L4CFG",}, |
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{0x600, "CLK2PWRDISC",}, |
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{0x0, "HOSTCLK1",}, |
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{0x900, "L4WAKEUP",}, |
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}; |
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static struct l3_flagmux_data omap_l3_flagmux_clk1 = { |
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.offset = 0x500, |
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.l3_targ = omap_l3_target_data_clk1, |
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.num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk1), |
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}; |
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static struct l3_target_data omap_l3_target_data_clk2[] = { |
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{0x500, "CORTEXM3",}, |
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{0x300, "DSS",}, |
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{0x100, "GPMC",}, |
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{0x400, "ISS",}, |
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{0x700, "IVAHD",}, |
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{0xD00, "AES1",}, |
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{0x900, "L4PER0",}, |
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{0x200, "OCMRAM",}, |
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{0x100, "GPMCsERROR",}, |
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{0x600, "SGX",}, |
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{0x800, "SL2",}, |
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{0x1600, "C2C",}, |
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{0x1100, "PWRDISCCLK1",}, |
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{0xF00, "SHA1",}, |
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{0xE00, "AES2",}, |
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{0xC00, "L4PER3",}, |
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{0xA00, "L4PER1",}, |
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{0xB00, "L4PER2",}, |
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{0x0, "HOSTCLK2",}, |
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{0x1800, "CAL",}, |
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{0x1700, "LLI",}, |
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}; |
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static struct l3_flagmux_data omap_l3_flagmux_clk2 = { |
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.offset = 0x1000, |
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.l3_targ = omap_l3_target_data_clk2, |
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.num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk2), |
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}; |
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static struct l3_target_data omap4_l3_target_data_clk3[] = { |
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{0x0100, "DEBUGSS",}, |
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}; |
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static struct l3_flagmux_data omap4_l3_flagmux_clk3 = { |
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.offset = 0x0200, |
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.l3_targ = omap4_l3_target_data_clk3, |
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.num_targ_data = ARRAY_SIZE(omap4_l3_target_data_clk3), |
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}; |
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static struct l3_masters_data omap_l3_masters[] = { |
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{ 0x00, "MPU"}, |
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{ 0x04, "CS_ADP"}, |
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{ 0x05, "xxx"}, |
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{ 0x08, "DSP"}, |
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{ 0x0C, "IVAHD"}, |
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{ 0x10, "ISS"}, |
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{ 0x11, "DucatiM3"}, |
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{ 0x12, "FaceDetect"}, |
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{ 0x14, "SDMA_Rd"}, |
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{ 0x15, "SDMA_Wr"}, |
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{ 0x16, "xxx"}, |
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{ 0x17, "xxx"}, |
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{ 0x18, "SGX"}, |
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{ 0x1C, "DSS"}, |
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{ 0x20, "C2C"}, |
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{ 0x22, "xxx"}, |
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{ 0x23, "xxx"}, |
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{ 0x24, "HSI"}, |
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{ 0x28, "MMC1"}, |
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{ 0x29, "MMC2"}, |
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{ 0x2A, "MMC6"}, |
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{ 0x2C, "UNIPRO1"}, |
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{ 0x30, "USBHOSTHS"}, |
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{ 0x31, "USBOTGHS"}, |
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{ 0x32, "USBHOSTFS"} |
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}; |
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static struct l3_flagmux_data *omap4_l3_flagmux[] = { |
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&omap_l3_flagmux_clk1, |
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&omap_l3_flagmux_clk2, |
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&omap4_l3_flagmux_clk3, |
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}; |
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static const struct omap_l3 omap4_l3_data = { |
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.l3_flagmux = omap4_l3_flagmux, |
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.num_modules = ARRAY_SIZE(omap4_l3_flagmux), |
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.l3_masters = omap_l3_masters, |
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.num_masters = ARRAY_SIZE(omap_l3_masters), |
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/* The 6 MSBs of register field used to distinguish initiator */ |
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.mst_addr_mask = 0xFC, |
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}; |
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/* OMAP5 data */ |
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static struct l3_target_data omap5_l3_target_data_clk3[] = { |
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{0x0100, "L3INSTR",}, |
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{0x0300, "DEBUGSS",}, |
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{0x0, "HOSTCLK3",}, |
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}; |
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static struct l3_flagmux_data omap5_l3_flagmux_clk3 = { |
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.offset = 0x0200, |
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.l3_targ = omap5_l3_target_data_clk3, |
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.num_targ_data = ARRAY_SIZE(omap5_l3_target_data_clk3), |
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}; |
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static struct l3_flagmux_data *omap5_l3_flagmux[] = { |
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&omap_l3_flagmux_clk1, |
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&omap_l3_flagmux_clk2, |
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&omap5_l3_flagmux_clk3, |
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}; |
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static const struct omap_l3 omap5_l3_data = { |
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.l3_flagmux = omap5_l3_flagmux, |
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.num_modules = ARRAY_SIZE(omap5_l3_flagmux), |
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.l3_masters = omap_l3_masters, |
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.num_masters = ARRAY_SIZE(omap_l3_masters), |
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/* The 6 MSBs of register field used to distinguish initiator */ |
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.mst_addr_mask = 0x7E0, |
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}; |
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/* DRA7 data */ |
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static struct l3_target_data dra_l3_target_data_clk1[] = { |
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{0x2a00, "AES1",}, |
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{0x0200, "DMM_P1",}, |
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{0x0600, "DSP2_SDMA",}, |
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{0x0b00, "EVE2",}, |
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{0x1300, "DMM_P2",}, |
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{0x2c00, "AES2",}, |
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{0x0300, "DSP1_SDMA",}, |
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{0x0a00, "EVE1",}, |
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{0x0c00, "EVE3",}, |
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{0x0d00, "EVE4",}, |
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{0x2900, "DSS",}, |
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{0x0100, "GPMC",}, |
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{0x3700, "PCIE1",}, |
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{0x1600, "IVA_CONFIG",}, |
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{0x1800, "IVA_SL2IF",}, |
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{0x0500, "L4_CFG",}, |
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{0x1d00, "L4_WKUP",}, |
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{0x3800, "PCIE2",}, |
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{0x3300, "SHA2_1",}, |
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{0x1200, "GPU",}, |
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{0x1000, "IPU1",}, |
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{0x1100, "IPU2",}, |
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{0x2000, "TPCC_EDMA",}, |
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{0x2e00, "TPTC1_EDMA",}, |
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{0x2b00, "TPTC2_EDMA",}, |
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{0x0700, "VCP1",}, |
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{0x2500, "L4_PER2_P3",}, |
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{0x0e00, "L4_PER3_P3",}, |
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{0x2200, "MMU1",}, |
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{0x1400, "PRUSS1",}, |
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{0x1500, "PRUSS2"}, |
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{0x0800, "VCP1",}, |
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}; |
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static struct l3_flagmux_data dra_l3_flagmux_clk1 = { |
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.offset = 0x803500, |
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.l3_targ = dra_l3_target_data_clk1, |
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.num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk1), |
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}; |
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static struct l3_target_data dra_l3_target_data_clk2[] = { |
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{0x0, "HOST CLK1",}, |
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{0x800000, "HOST CLK2",}, |
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{0xdead, L3_TARGET_NOT_SUPPORTED,}, |
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{0x3400, "SHA2_2",}, |
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{0x0900, "BB2D",}, |
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{0xdead, L3_TARGET_NOT_SUPPORTED,}, |
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{0x2100, "L4_PER1_P3",}, |
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{0x1c00, "L4_PER1_P1",}, |
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{0x1f00, "L4_PER1_P2",}, |
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{0x2300, "L4_PER2_P1",}, |
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{0x2400, "L4_PER2_P2",}, |
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{0x2600, "L4_PER3_P1",}, |
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{0x2700, "L4_PER3_P2",}, |
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{0x2f00, "MCASP1",}, |
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{0x3000, "MCASP2",}, |
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{0x3100, "MCASP3",}, |
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{0x2800, "MMU2",}, |
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{0x0f00, "OCMC_RAM1",}, |
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{0x1700, "OCMC_RAM2",}, |
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{0x1900, "OCMC_RAM3",}, |
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{0x1e00, "OCMC_ROM",}, |
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{0x3900, "QSPI",}, |
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}; |
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static struct l3_flagmux_data dra_l3_flagmux_clk2 = { |
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.offset = 0x803600, |
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.l3_targ = dra_l3_target_data_clk2, |
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.num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk2), |
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}; |
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static struct l3_target_data dra_l3_target_data_clk3[] = { |
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{0x0100, "L3_INSTR"}, |
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{0x0300, "DEBUGSS_CT_TBR"}, |
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{0x0, "HOST CLK3"}, |
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}; |
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static struct l3_flagmux_data dra_l3_flagmux_clk3 = { |
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.offset = 0x200, |
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.l3_targ = dra_l3_target_data_clk3, |
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.num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk3), |
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}; |
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static struct l3_masters_data dra_l3_masters[] = { |
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{ 0x0, "MPU" }, |
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{ 0x4, "CS_DAP" }, |
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{ 0x5, "IEEE1500_2_OCP" }, |
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{ 0x8, "DSP1_MDMA" }, |
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{ 0x9, "DSP1_CFG" }, |
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{ 0xA, "DSP1_DMA" }, |
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{ 0xB, "DSP2_MDMA" }, |
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{ 0xC, "DSP2_CFG" }, |
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{ 0xD, "DSP2_DMA" }, |
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{ 0xE, "IVA" }, |
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{ 0x10, "EVE1_P1" }, |
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{ 0x11, "EVE2_P1" }, |
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{ 0x12, "EVE3_P1" }, |
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{ 0x13, "EVE4_P1" }, |
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{ 0x14, "PRUSS1 PRU1" }, |
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{ 0x15, "PRUSS1 PRU2" }, |
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{ 0x16, "PRUSS2 PRU1" }, |
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{ 0x17, "PRUSS2 PRU2" }, |
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{ 0x18, "IPU1" }, |
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{ 0x19, "IPU2" }, |
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{ 0x1A, "SDMA" }, |
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{ 0x1B, "CDMA" }, |
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{ 0x1C, "TC1_EDMA" }, |
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{ 0x1D, "TC2_EDMA" }, |
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{ 0x20, "DSS" }, |
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{ 0x21, "MMU1" }, |
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{ 0x22, "PCIE1" }, |
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{ 0x23, "MMU2" }, |
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{ 0x24, "VIP1" }, |
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{ 0x25, "VIP2" }, |
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{ 0x26, "VIP3" }, |
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{ 0x27, "VPE" }, |
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{ 0x28, "GPU_P1" }, |
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{ 0x29, "BB2D" }, |
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{ 0x29, "GPU_P2" }, |
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{ 0x2B, "GMAC_SW" }, |
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{ 0x2C, "USB3" }, |
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{ 0x2D, "USB2_SS" }, |
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{ 0x2E, "USB2_ULPI_SS1" }, |
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{ 0x2F, "USB2_ULPI_SS2" }, |
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{ 0x30, "CSI2_1" }, |
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{ 0x31, "CSI2_2" }, |
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{ 0x33, "SATA" }, |
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{ 0x34, "EVE1_P2" }, |
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{ 0x35, "EVE2_P2" }, |
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{ 0x36, "EVE3_P2" }, |
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{ 0x37, "EVE4_P2" } |
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}; |
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static struct l3_flagmux_data *dra_l3_flagmux[] = { |
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&dra_l3_flagmux_clk1, |
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&dra_l3_flagmux_clk2, |
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&dra_l3_flagmux_clk3, |
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}; |
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static const struct omap_l3 dra_l3_data = { |
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.l3_base = { [1] = L3_BASE_IS_SUBMODULE }, |
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.l3_flagmux = dra_l3_flagmux, |
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.num_modules = ARRAY_SIZE(dra_l3_flagmux), |
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.l3_masters = dra_l3_masters, |
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.num_masters = ARRAY_SIZE(dra_l3_masters), |
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/* The 6 MSBs of register field used to distinguish initiator */ |
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.mst_addr_mask = 0xFC, |
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}; |
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|
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/* AM4372 data */ |
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static struct l3_target_data am4372_l3_target_data_200f[] = { |
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{0xf00, "EMIF",}, |
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{0x1200, "DES",}, |
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{0x400, "OCMCRAM",}, |
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{0x700, "TPTC0",}, |
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{0x800, "TPTC1",}, |
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{0x900, "TPTC2"}, |
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{0xb00, "TPCC",}, |
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{0xd00, "DEBUGSS",}, |
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{0xdead, L3_TARGET_NOT_SUPPORTED,}, |
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{0x200, "SHA",}, |
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{0xc00, "SGX530",}, |
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{0x500, "AES0",}, |
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{0xa00, "L4_FAST",}, |
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{0x300, "MPUSS_L2_RAM",}, |
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{0x100, "ICSS",}, |
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}; |
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static struct l3_flagmux_data am4372_l3_flagmux_200f = { |
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.offset = 0x1000, |
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.l3_targ = am4372_l3_target_data_200f, |
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.num_targ_data = ARRAY_SIZE(am4372_l3_target_data_200f), |
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}; |
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static struct l3_target_data am4372_l3_target_data_100s[] = { |
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{0x100, "L4_PER_0",}, |
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{0x200, "L4_PER_1",}, |
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{0x300, "L4_PER_2",}, |
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{0x400, "L4_PER_3",}, |
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{0x800, "McASP0",}, |
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{0x900, "McASP1",}, |
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{0xC00, "MMCHS2",}, |
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{0x700, "GPMC",}, |
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{0xD00, "L4_FW",}, |
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{0xdead, L3_TARGET_NOT_SUPPORTED,}, |
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{0x500, "ADCTSC",}, |
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{0xE00, "L4_WKUP",}, |
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{0xA00, "MAG_CARD",}, |
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}; |
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|
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static struct l3_flagmux_data am4372_l3_flagmux_100s = { |
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.offset = 0x600, |
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.l3_targ = am4372_l3_target_data_100s, |
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.num_targ_data = ARRAY_SIZE(am4372_l3_target_data_100s), |
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}; |
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static struct l3_masters_data am4372_l3_masters[] = { |
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{ 0x0, "M1 (128-bit)"}, |
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{ 0x1, "M2 (64-bit)"}, |
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{ 0x4, "DAP"}, |
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{ 0x5, "P1500"}, |
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{ 0xC, "ICSS0"}, |
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{ 0xD, "ICSS1"}, |
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{ 0x14, "Wakeup Processor"}, |
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{ 0x18, "TPTC0 Read"}, |
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{ 0x19, "TPTC0 Write"}, |
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{ 0x1A, "TPTC1 Read"}, |
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{ 0x1B, "TPTC1 Write"}, |
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{ 0x1C, "TPTC2 Read"}, |
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{ 0x1D, "TPTC2 Write"}, |
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{ 0x20, "SGX530"}, |
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{ 0x21, "OCP WP Traffic Probe"}, |
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{ 0x22, "OCP WP DMA Profiling"}, |
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{ 0x23, "OCP WP Event Trace"}, |
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{ 0x25, "DSS"}, |
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{ 0x28, "Crypto DMA RD"}, |
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{ 0x29, "Crypto DMA WR"}, |
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{ 0x2C, "VPFE0"}, |
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{ 0x2D, "VPFE1"}, |
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{ 0x30, "GEMAC"}, |
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{ 0x34, "USB0 RD"}, |
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{ 0x35, "USB0 WR"}, |
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{ 0x36, "USB1 RD"}, |
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{ 0x37, "USB1 WR"}, |
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}; |
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|
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static struct l3_flagmux_data *am4372_l3_flagmux[] = { |
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&am4372_l3_flagmux_200f, |
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&am4372_l3_flagmux_100s, |
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}; |
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|
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static const struct omap_l3 am4372_l3_data = { |
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.l3_flagmux = am4372_l3_flagmux, |
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.num_modules = ARRAY_SIZE(am4372_l3_flagmux), |
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.l3_masters = am4372_l3_masters, |
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.num_masters = ARRAY_SIZE(am4372_l3_masters), |
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/* All 6 bits of register field used to distinguish initiator */ |
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.mst_addr_mask = 0x3F, |
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}; |
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|
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#endif /* __OMAP_L3_NOC_H */
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|
|