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493 lines
13 KiB
493 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* pata_serverworks.c - Serverworks PATA for new ATA layer |
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* (C) 2005 Red Hat Inc |
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* (C) 2010 Bartlomiej Zolnierkiewicz |
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* |
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* based upon |
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* |
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* serverworks.c |
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* |
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* Copyright (C) 1998-2000 Michel Aubry |
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* Copyright (C) 1998-2000 Andrzej Krzysztofowicz |
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* Copyright (C) 1998-2000 Andre Hedrick <[email protected]> |
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* Portions copyright (c) 2001 Sun Microsystems |
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* |
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* |
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* RCC/ServerWorks IDE driver for Linux |
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* |
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* OSB4: `Open South Bridge' IDE Interface (fn 1) |
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* supports UDMA mode 2 (33 MB/s) |
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* |
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* CSB5: `Champion South Bridge' IDE Interface (fn 1) |
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* all revisions support UDMA mode 4 (66 MB/s) |
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* revision A2.0 and up support UDMA mode 5 (100 MB/s) |
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* |
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* *** The CSB5 does not provide ANY register *** |
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* *** to detect 80-conductor cable presence. *** |
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* |
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* CSB6: `Champion South Bridge' IDE Interface (optional: third channel) |
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* |
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* Documentation: |
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* Available under NDA only. Errata info very hard to get. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/blkdev.h> |
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#include <linux/delay.h> |
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#include <scsi/scsi_host.h> |
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#include <linux/libata.h> |
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#define DRV_NAME "pata_serverworks" |
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#define DRV_VERSION "0.4.3" |
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#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */ |
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#define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */ |
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/* Seagate Barracuda ATA IV Family drives in UDMA mode 5 |
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* can overrun their FIFOs when used with the CSB5 */ |
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static const char *csb_bad_ata100[] = { |
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"ST320011A", |
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"ST340016A", |
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"ST360021A", |
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"ST380021A", |
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NULL |
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}; |
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/** |
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* oem_cable - Dell/Sun serverworks cable detection |
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* @ap: ATA port to do cable detect |
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* |
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* Dell PowerEdge and Sun Cobalt 'Alpine' hide the 40/80 pin select |
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* for their interfaces in the top two bits of the subsystem ID. |
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*/ |
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static int oem_cable(struct ata_port *ap) |
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{ |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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if (pdev->subsystem_device & (1 << (ap->port_no + 14))) |
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return ATA_CBL_PATA80; |
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return ATA_CBL_PATA40; |
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} |
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struct sv_cable_table { |
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int device; |
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int subvendor; |
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int (*cable_detect)(struct ata_port *ap); |
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}; |
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static struct sv_cable_table cable_detect[] = { |
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{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_DELL, oem_cable }, |
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{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_VENDOR_ID_DELL, oem_cable }, |
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{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_SUN, oem_cable }, |
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{ PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, ata_cable_40wire }, |
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{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, ata_cable_unknown }, |
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{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, ata_cable_unknown }, |
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{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, ata_cable_unknown }, |
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{ PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, ata_cable_unknown }, |
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{ } |
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}; |
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/** |
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* serverworks_cable_detect - cable detection |
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* @ap: ATA port |
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* |
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* Perform cable detection according to the device and subvendor |
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* identifications |
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*/ |
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static int serverworks_cable_detect(struct ata_port *ap) |
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{ |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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struct sv_cable_table *cb = cable_detect; |
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while(cb->device) { |
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if (cb->device == pdev->device && |
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(cb->subvendor == pdev->subsystem_vendor || |
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cb->subvendor == PCI_ANY_ID)) { |
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return cb->cable_detect(ap); |
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} |
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cb++; |
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} |
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BUG(); |
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return -1; /* kill compiler warning */ |
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} |
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/** |
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* serverworks_is_csb - Check for CSB or OSB |
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* @pdev: PCI device to check |
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* |
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* Returns true if the device being checked is known to be a CSB |
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* series device. |
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*/ |
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static u8 serverworks_is_csb(struct pci_dev *pdev) |
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{ |
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switch (pdev->device) { |
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case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: |
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case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: |
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case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: |
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case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE: |
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return 1; |
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default: |
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break; |
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} |
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return 0; |
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} |
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/** |
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* serverworks_osb4_filter - mode selection filter |
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* @adev: ATA device |
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* @mask: Mask of proposed modes |
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* |
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* Filter the offered modes for the device to apply controller |
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* specific rules. OSB4 requires no UDMA for disks due to a FIFO |
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* bug we hit. |
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*/ |
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static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask) |
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{ |
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if (adev->class == ATA_DEV_ATA) |
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mask &= ~ATA_MASK_UDMA; |
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return mask; |
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} |
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/** |
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* serverworks_csb_filter - mode selection filter |
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* @adev: ATA device |
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* @mask: Mask of proposed modes |
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* |
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* Check the blacklist and disable UDMA5 if matched |
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*/ |
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static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask) |
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{ |
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const char *p; |
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char model_num[ATA_ID_PROD_LEN + 1]; |
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int i; |
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/* Disk, UDMA */ |
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if (adev->class != ATA_DEV_ATA) |
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return mask; |
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/* Actually do need to check */ |
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ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num)); |
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for (i = 0; (p = csb_bad_ata100[i]) != NULL; i++) { |
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if (!strcmp(p, model_num)) |
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mask &= ~(0xE0 << ATA_SHIFT_UDMA); |
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} |
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return mask; |
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} |
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/** |
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* serverworks_set_piomode - set initial PIO mode data |
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* @ap: ATA interface |
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* @adev: ATA device |
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* |
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* Program the OSB4/CSB5 timing registers for PIO. The PIO register |
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* load is done as a simple lookup. |
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*/ |
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static void serverworks_set_piomode(struct ata_port *ap, struct ata_device *adev) |
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{ |
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static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; |
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int offset = 1 + 2 * ap->port_no - adev->devno; |
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int devbits = (2 * ap->port_no + adev->devno) * 4; |
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u16 csb5_pio; |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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int pio = adev->pio_mode - XFER_PIO_0; |
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pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]); |
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/* The OSB4 just requires the timing but the CSB series want the |
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mode number as well */ |
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if (serverworks_is_csb(pdev)) { |
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pci_read_config_word(pdev, 0x4A, &csb5_pio); |
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csb5_pio &= ~(0x0F << devbits); |
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pci_write_config_word(pdev, 0x4A, csb5_pio | (pio << devbits)); |
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} |
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} |
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/** |
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* serverworks_set_dmamode - set initial DMA mode data |
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* @ap: ATA interface |
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* @adev: ATA device |
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* |
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* Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5 |
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* chipset. The MWDMA mode values are pulled from a lookup table |
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* while the chipset uses mode number for UDMA. |
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*/ |
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static void serverworks_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
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{ |
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static const u8 dma_mode[] = { 0x77, 0x21, 0x20 }; |
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int offset = 1 + 2 * ap->port_no - adev->devno; |
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int devbits = 2 * ap->port_no + adev->devno; |
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u8 ultra; |
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u8 ultra_cfg; |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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pci_read_config_byte(pdev, 0x54, &ultra_cfg); |
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pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra); |
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ultra &= ~(0x0F << (adev->devno * 4)); |
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if (adev->dma_mode >= XFER_UDMA_0) { |
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pci_write_config_byte(pdev, 0x44 + offset, 0x20); |
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ultra |= (adev->dma_mode - XFER_UDMA_0) |
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<< (adev->devno * 4); |
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ultra_cfg |= (1 << devbits); |
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} else { |
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pci_write_config_byte(pdev, 0x44 + offset, |
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dma_mode[adev->dma_mode - XFER_MW_DMA_0]); |
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ultra_cfg &= ~(1 << devbits); |
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} |
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pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra); |
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pci_write_config_byte(pdev, 0x54, ultra_cfg); |
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} |
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static struct scsi_host_template serverworks_osb4_sht = { |
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ATA_BMDMA_SHT(DRV_NAME), |
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.sg_tablesize = LIBATA_DUMB_MAX_PRD, |
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}; |
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static struct scsi_host_template serverworks_csb_sht = { |
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ATA_BMDMA_SHT(DRV_NAME), |
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}; |
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static struct ata_port_operations serverworks_osb4_port_ops = { |
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.inherits = &ata_bmdma_port_ops, |
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.qc_prep = ata_bmdma_dumb_qc_prep, |
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.cable_detect = serverworks_cable_detect, |
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.mode_filter = serverworks_osb4_filter, |
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.set_piomode = serverworks_set_piomode, |
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.set_dmamode = serverworks_set_dmamode, |
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}; |
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static struct ata_port_operations serverworks_csb_port_ops = { |
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.inherits = &serverworks_osb4_port_ops, |
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.qc_prep = ata_bmdma_qc_prep, |
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.mode_filter = serverworks_csb_filter, |
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}; |
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static int serverworks_fixup_osb4(struct pci_dev *pdev) |
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{ |
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u32 reg; |
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struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
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PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL); |
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if (isa_dev) { |
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pci_read_config_dword(isa_dev, 0x64, ®); |
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reg &= ~0x00002000; /* disable 600ns interrupt mask */ |
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if (!(reg & 0x00004000)) |
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printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n"); |
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reg |= 0x00004000; /* enable UDMA/33 support */ |
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pci_write_config_dword(isa_dev, 0x64, reg); |
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pci_dev_put(isa_dev); |
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return 0; |
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} |
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printk(KERN_WARNING DRV_NAME ": Unable to find bridge.\n"); |
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return -ENODEV; |
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} |
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static int serverworks_fixup_csb(struct pci_dev *pdev) |
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{ |
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u8 btr; |
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/* Third Channel Test */ |
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if (!(PCI_FUNC(pdev->devfn) & 1)) { |
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struct pci_dev * findev = NULL; |
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u32 reg4c = 0; |
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findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
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PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL); |
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if (findev) { |
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pci_read_config_dword(findev, 0x4C, ®4c); |
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reg4c &= ~0x000007FF; |
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reg4c |= 0x00000040; |
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reg4c |= 0x00000020; |
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pci_write_config_dword(findev, 0x4C, reg4c); |
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pci_dev_put(findev); |
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} |
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} else { |
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struct pci_dev * findev = NULL; |
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u8 reg41 = 0; |
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findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
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PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL); |
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if (findev) { |
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pci_read_config_byte(findev, 0x41, ®41); |
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reg41 &= ~0x40; |
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pci_write_config_byte(findev, 0x41, reg41); |
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pci_dev_put(findev); |
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} |
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} |
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/* setup the UDMA Control register |
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* |
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* 1. clear bit 6 to enable DMA |
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* 2. enable DMA modes with bits 0-1 |
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* 00 : legacy |
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* 01 : udma2 |
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* 10 : udma2/udma4 |
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* 11 : udma2/udma4/udma5 |
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*/ |
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pci_read_config_byte(pdev, 0x5A, &btr); |
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btr &= ~0x40; |
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if (!(PCI_FUNC(pdev->devfn) & 1)) |
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btr |= 0x2; |
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else |
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btr |= (pdev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2; |
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pci_write_config_byte(pdev, 0x5A, btr); |
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return btr; |
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} |
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static void serverworks_fixup_ht1000(struct pci_dev *pdev) |
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{ |
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u8 btr; |
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/* Setup HT1000 SouthBridge Controller - Single Channel Only */ |
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pci_read_config_byte(pdev, 0x5A, &btr); |
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btr &= ~0x40; |
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btr |= 0x3; |
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pci_write_config_byte(pdev, 0x5A, btr); |
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} |
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static int serverworks_fixup(struct pci_dev *pdev) |
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{ |
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int rc = 0; |
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/* Force master latency timer to 64 PCI clocks */ |
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pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40); |
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switch (pdev->device) { |
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case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE: |
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rc = serverworks_fixup_osb4(pdev); |
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break; |
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case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: |
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ata_pci_bmdma_clear_simplex(pdev); |
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fallthrough; |
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case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: |
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case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: |
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rc = serverworks_fixup_csb(pdev); |
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break; |
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case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE: |
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serverworks_fixup_ht1000(pdev); |
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break; |
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} |
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return rc; |
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} |
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static int serverworks_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
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{ |
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static const struct ata_port_info info[4] = { |
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{ /* OSB4 */ |
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.flags = ATA_FLAG_SLAVE_POSS, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, |
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.udma_mask = ATA_UDMA2, |
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.port_ops = &serverworks_osb4_port_ops |
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}, { /* OSB4 no UDMA */ |
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.flags = ATA_FLAG_SLAVE_POSS, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, |
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/* No UDMA */ |
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.port_ops = &serverworks_osb4_port_ops |
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}, { /* CSB5 */ |
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.flags = ATA_FLAG_SLAVE_POSS, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, |
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.udma_mask = ATA_UDMA4, |
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.port_ops = &serverworks_csb_port_ops |
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}, { /* CSB5 - later revisions*/ |
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.flags = ATA_FLAG_SLAVE_POSS, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, |
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.udma_mask = ATA_UDMA5, |
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.port_ops = &serverworks_csb_port_ops |
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} |
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}; |
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const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL }; |
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struct scsi_host_template *sht = &serverworks_csb_sht; |
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int rc; |
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rc = pcim_enable_device(pdev); |
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if (rc) |
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return rc; |
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rc = serverworks_fixup(pdev); |
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/* OSB4 : South Bridge and IDE */ |
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if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { |
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/* Select non UDMA capable OSB4 if we can't do fixups */ |
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if (rc < 0) |
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ppi[0] = &info[1]; |
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sht = &serverworks_osb4_sht; |
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} |
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/* setup CSB5/CSB6 : South Bridge and IDE option RAID */ |
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else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) || |
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(pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || |
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(pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) { |
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/* If the returned btr is the newer revision then |
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select the right info block */ |
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if (rc == 3) |
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ppi[0] = &info[3]; |
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/* Is this the 3rd channel CSB6 IDE ? */ |
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if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) |
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ppi[1] = &ata_dummy_port_info; |
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} |
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return ata_pci_bmdma_init_one(pdev, ppi, sht, NULL, 0); |
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} |
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#ifdef CONFIG_PM_SLEEP |
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static int serverworks_reinit_one(struct pci_dev *pdev) |
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{ |
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struct ata_host *host = pci_get_drvdata(pdev); |
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int rc; |
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rc = ata_pci_device_do_resume(pdev); |
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if (rc) |
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return rc; |
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(void)serverworks_fixup(pdev); |
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ata_host_resume(host); |
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return 0; |
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} |
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#endif |
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static const struct pci_device_id serverworks[] = { |
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{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0}, |
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{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2}, |
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{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2}, |
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{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2}, |
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{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2}, |
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{ }, |
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}; |
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static struct pci_driver serverworks_pci_driver = { |
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.name = DRV_NAME, |
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.id_table = serverworks, |
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.probe = serverworks_init_one, |
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.remove = ata_pci_remove_one, |
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#ifdef CONFIG_PM_SLEEP |
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.suspend = ata_pci_device_suspend, |
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.resume = serverworks_reinit_one, |
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#endif |
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}; |
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module_pci_driver(serverworks_pci_driver); |
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MODULE_AUTHOR("Alan Cox"); |
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MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6"); |
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MODULE_LICENSE("GPL"); |
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MODULE_DEVICE_TABLE(pci, serverworks); |
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MODULE_VERSION(DRV_VERSION);
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