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422 lines
11 KiB
422 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* pata_ns87415.c - NS87415 (and PARISC SUPERIO 87560) PATA |
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* |
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* (C) 2005 Red Hat <[email protected]> |
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* |
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* This is a fairly generic MWDMA controller. It has some limitations |
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* as it requires timing reloads on PIO/DMA transitions but it is otherwise |
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* fairly well designed. |
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* |
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* This driver assumes the firmware has left the chip in a valid ST506 |
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* compliant state, either legacy IRQ 14/15 or native INTA shared. You |
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* may need to add platform code if your system fails to do this. |
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* |
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* The same cell appears in the 87560 controller used by some PARISC |
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* systems. This has its own special mountain of errata. |
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* |
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* TODO: |
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* Get someone to test on SPARC |
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* Implement lazy pio/dma switching for better performance |
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* 8bit shared timing. |
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* See if we need to kill the FIFO for ATAPI |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/blkdev.h> |
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#include <linux/delay.h> |
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#include <linux/device.h> |
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#include <scsi/scsi_host.h> |
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#include <linux/libata.h> |
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#include <linux/ata.h> |
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#define DRV_NAME "pata_ns87415" |
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#define DRV_VERSION "0.0.1" |
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/** |
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* ns87415_set_mode - Initialize host controller mode timings |
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* @ap: Port whose timings we are configuring |
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* @adev: Device whose timings we are configuring |
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* @mode: Mode to set |
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* |
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* Program the mode registers for this controller, channel and |
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* device. Because the chip is quite an old design we have to do this |
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* for PIO/DMA switches. |
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* |
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* LOCKING: |
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* None (inherited from caller). |
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*/ |
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static void ns87415_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode) |
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{ |
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struct pci_dev *dev = to_pci_dev(ap->host->dev); |
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int unit = 2 * ap->port_no + adev->devno; |
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int timing = 0x44 + 2 * unit; |
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unsigned long T = 1000000000 / 33333; /* PCI clocks */ |
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struct ata_timing t; |
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u16 clocking; |
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u8 iordy; |
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u8 status; |
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/* Timing register format is 17 - low nybble read timing with |
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the high nybble being 16 - x for recovery time in PCI clocks */ |
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ata_timing_compute(adev, adev->pio_mode, &t, T, 0); |
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clocking = 17 - clamp_val(t.active, 2, 17); |
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clocking |= (16 - clamp_val(t.recover, 1, 16)) << 4; |
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/* Use the same timing for read and write bytes */ |
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clocking |= (clocking << 8); |
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pci_write_config_word(dev, timing, clocking); |
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/* Set the IORDY enable versus DMA enable on or off properly */ |
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pci_read_config_byte(dev, 0x42, &iordy); |
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iordy &= ~(1 << (4 + unit)); |
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if (mode >= XFER_MW_DMA_0 || !ata_pio_need_iordy(adev)) |
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iordy |= (1 << (4 + unit)); |
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/* Paranoia: We shouldn't ever get here with busy write buffers |
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but if so wait */ |
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pci_read_config_byte(dev, 0x43, &status); |
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while (status & 0x03) { |
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udelay(1); |
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pci_read_config_byte(dev, 0x43, &status); |
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} |
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/* Flip the IORDY/DMA bits now we are sure the write buffers are |
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clear */ |
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pci_write_config_byte(dev, 0x42, iordy); |
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/* TODO: Set byte 54 command timing to the best 8bit |
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mode shared by all four devices */ |
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} |
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/** |
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* ns87415_set_piomode - Initialize host controller PATA PIO timings |
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* @ap: Port whose timings we are configuring |
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* @adev: Device to program |
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* |
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* Set PIO mode for device, in host controller PCI config space. |
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* |
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* LOCKING: |
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* None (inherited from caller). |
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*/ |
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static void ns87415_set_piomode(struct ata_port *ap, struct ata_device *adev) |
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{ |
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ns87415_set_mode(ap, adev, adev->pio_mode); |
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} |
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/** |
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* ns87415_bmdma_setup - Set up DMA |
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* @qc: Command block |
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* |
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* Set up for bus masterng DMA. We have to do this ourselves |
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* rather than use the helper due to a chip erratum |
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*/ |
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static void ns87415_bmdma_setup(struct ata_queued_cmd *qc) |
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{ |
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struct ata_port *ap = qc->ap; |
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unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); |
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u8 dmactl; |
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/* load PRD table addr. */ |
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mb(); /* make sure PRD table writes are visible to controller */ |
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iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); |
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/* specify data direction, triple-check start bit is clear */ |
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dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
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dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); |
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/* Due to an erratum we need to write these bits to the wrong |
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place - which does save us an I/O bizarrely */ |
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dmactl |= ATA_DMA_INTR | ATA_DMA_ERR; |
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if (!rw) |
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dmactl |= ATA_DMA_WR; |
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iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
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/* issue r/w command */ |
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ap->ops->sff_exec_command(ap, &qc->tf); |
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} |
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/** |
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* ns87415_bmdma_start - Begin DMA transfer |
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* @qc: Command block |
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* |
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* Switch the timings for the chip and set up for a DMA transfer |
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* before the DMA burst begins. |
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* |
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* FIXME: We should do lazy switching on bmdma_start versus |
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* ata_pio_data_xfer for better performance. |
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*/ |
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static void ns87415_bmdma_start(struct ata_queued_cmd *qc) |
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{ |
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ns87415_set_mode(qc->ap, qc->dev, qc->dev->dma_mode); |
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ata_bmdma_start(qc); |
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} |
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/** |
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* ns87415_bmdma_stop - End DMA transfer |
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* @qc: Command block |
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* |
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* End DMA mode and switch the controller back into PIO mode |
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*/ |
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static void ns87415_bmdma_stop(struct ata_queued_cmd *qc) |
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{ |
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ata_bmdma_stop(qc); |
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ns87415_set_mode(qc->ap, qc->dev, qc->dev->pio_mode); |
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} |
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/** |
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* ns87415_irq_clear - Clear interrupt |
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* @ap: Channel to clear |
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* |
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* Erratum: Due to a chip bug regisers 02 and 0A bit 1 and 2 (the |
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* error bits) are reset by writing to register 00 or 08. |
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*/ |
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static void ns87415_irq_clear(struct ata_port *ap) |
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{ |
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void __iomem *mmio = ap->ioaddr.bmdma_addr; |
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if (!mmio) |
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return; |
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iowrite8((ioread8(mmio + ATA_DMA_CMD) | ATA_DMA_INTR | ATA_DMA_ERR), |
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mmio + ATA_DMA_CMD); |
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} |
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/** |
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* ns87415_check_atapi_dma - ATAPI DMA filter |
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* @qc: Command block |
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* |
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* Disable ATAPI DMA (for now). We may be able to do DMA if we |
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* kill the prefetching. This isn't clear. |
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*/ |
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static int ns87415_check_atapi_dma(struct ata_queued_cmd *qc) |
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{ |
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return -EOPNOTSUPP; |
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} |
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#if defined(CONFIG_SUPERIO) |
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/* SUPERIO 87560 is a PoS chip that NatSem denies exists. |
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* Unfortunately, it's built-in on all Astro-based PA-RISC workstations |
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* which use the integrated NS87514 cell for CD-ROM support. |
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* i.e we have to support for CD-ROM installs. |
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* See drivers/parisc/superio.c for more gory details. |
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* |
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* Workarounds taken from drivers/ide/pci/ns87415.c |
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*/ |
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#include <asm/superio.h> |
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#define SUPERIO_IDE_MAX_RETRIES 25 |
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/** |
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* ns87560_read_buggy - workaround buggy Super I/O chip |
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* @port: Port to read |
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* |
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* Work around chipset problems in the 87560 SuperIO chip |
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*/ |
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static u8 ns87560_read_buggy(void __iomem *port) |
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{ |
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u8 tmp; |
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int retries = SUPERIO_IDE_MAX_RETRIES; |
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do { |
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tmp = ioread8(port); |
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if (tmp != 0) |
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return tmp; |
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udelay(50); |
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} while(retries-- > 0); |
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return tmp; |
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} |
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/** |
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* ns87560_check_status |
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* @ap: channel to check |
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* |
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* Return the status of the channel working around the |
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* 87560 flaws. |
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*/ |
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static u8 ns87560_check_status(struct ata_port *ap) |
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{ |
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return ns87560_read_buggy(ap->ioaddr.status_addr); |
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} |
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/** |
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* ns87560_tf_read - input device's ATA taskfile shadow registers |
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* @ap: Port from which input is read |
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* @tf: ATA taskfile register set for storing input |
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* |
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* Reads ATA taskfile registers for currently-selected device |
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* into @tf. Work around the 87560 bugs. |
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* |
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* LOCKING: |
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* Inherited from caller. |
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*/ |
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void ns87560_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
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{ |
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struct ata_ioports *ioaddr = &ap->ioaddr; |
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tf->command = ns87560_check_status(ap); |
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tf->feature = ioread8(ioaddr->error_addr); |
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tf->nsect = ioread8(ioaddr->nsect_addr); |
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tf->lbal = ioread8(ioaddr->lbal_addr); |
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tf->lbam = ioread8(ioaddr->lbam_addr); |
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tf->lbah = ioread8(ioaddr->lbah_addr); |
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tf->device = ns87560_read_buggy(ioaddr->device_addr); |
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if (tf->flags & ATA_TFLAG_LBA48) { |
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iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); |
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tf->hob_feature = ioread8(ioaddr->error_addr); |
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tf->hob_nsect = ioread8(ioaddr->nsect_addr); |
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tf->hob_lbal = ioread8(ioaddr->lbal_addr); |
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tf->hob_lbam = ioread8(ioaddr->lbam_addr); |
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tf->hob_lbah = ioread8(ioaddr->lbah_addr); |
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iowrite8(tf->ctl, ioaddr->ctl_addr); |
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ap->last_ctl = tf->ctl; |
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} |
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} |
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/** |
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* ns87560_bmdma_status |
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* @ap: channel to check |
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* |
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* Return the DMA status of the channel working around the |
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* 87560 flaws. |
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*/ |
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static u8 ns87560_bmdma_status(struct ata_port *ap) |
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{ |
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return ns87560_read_buggy(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); |
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} |
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#endif /* 87560 SuperIO Support */ |
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static struct ata_port_operations ns87415_pata_ops = { |
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.inherits = &ata_bmdma_port_ops, |
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.check_atapi_dma = ns87415_check_atapi_dma, |
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.bmdma_setup = ns87415_bmdma_setup, |
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.bmdma_start = ns87415_bmdma_start, |
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.bmdma_stop = ns87415_bmdma_stop, |
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.sff_irq_clear = ns87415_irq_clear, |
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.cable_detect = ata_cable_40wire, |
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.set_piomode = ns87415_set_piomode, |
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}; |
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#if defined(CONFIG_SUPERIO) |
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static struct ata_port_operations ns87560_pata_ops = { |
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.inherits = &ns87415_pata_ops, |
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.sff_tf_read = ns87560_tf_read, |
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.sff_check_status = ns87560_check_status, |
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.bmdma_status = ns87560_bmdma_status, |
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}; |
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#endif |
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static struct scsi_host_template ns87415_sht = { |
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ATA_BMDMA_SHT(DRV_NAME), |
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}; |
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static void ns87415_fixup(struct pci_dev *pdev) |
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{ |
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/* Select 512 byte sectors */ |
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pci_write_config_byte(pdev, 0x55, 0xEE); |
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/* Select PIO0 8bit clocking */ |
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pci_write_config_byte(pdev, 0x54, 0xB7); |
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} |
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/** |
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* ns87415_init_one - Register 87415 ATA PCI device with kernel services |
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* @pdev: PCI device to register |
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* @ent: Entry in ns87415_pci_tbl matching with @pdev |
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* |
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* Called from kernel PCI layer. We probe for combined mode (sigh), |
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* and then hand over control to libata, for it to do the rest. |
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* |
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* LOCKING: |
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* Inherited from PCI layer (may sleep). |
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* |
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* RETURNS: |
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* Zero on success, or -ERRNO value. |
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*/ |
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static int ns87415_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
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{ |
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static const struct ata_port_info info = { |
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.flags = ATA_FLAG_SLAVE_POSS, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, |
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.port_ops = &ns87415_pata_ops, |
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}; |
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const struct ata_port_info *ppi[] = { &info, NULL }; |
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int rc; |
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#if defined(CONFIG_SUPERIO) |
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static const struct ata_port_info info87560 = { |
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.flags = ATA_FLAG_SLAVE_POSS, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, |
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.port_ops = &ns87560_pata_ops, |
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}; |
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if (PCI_SLOT(pdev->devfn) == 0x0E) |
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ppi[0] = &info87560; |
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#endif |
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ata_print_version_once(&pdev->dev, DRV_VERSION); |
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rc = pcim_enable_device(pdev); |
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if (rc) |
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return rc; |
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ns87415_fixup(pdev); |
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return ata_pci_bmdma_init_one(pdev, ppi, &ns87415_sht, NULL, 0); |
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} |
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static const struct pci_device_id ns87415_pci_tbl[] = { |
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{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), }, |
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{ } /* terminate list */ |
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}; |
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#ifdef CONFIG_PM_SLEEP |
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static int ns87415_reinit_one(struct pci_dev *pdev) |
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{ |
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struct ata_host *host = pci_get_drvdata(pdev); |
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int rc; |
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rc = ata_pci_device_do_resume(pdev); |
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if (rc) |
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return rc; |
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ns87415_fixup(pdev); |
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ata_host_resume(host); |
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return 0; |
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} |
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#endif |
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static struct pci_driver ns87415_pci_driver = { |
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.name = DRV_NAME, |
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.id_table = ns87415_pci_tbl, |
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.probe = ns87415_init_one, |
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.remove = ata_pci_remove_one, |
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#ifdef CONFIG_PM_SLEEP |
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.suspend = ata_pci_device_suspend, |
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.resume = ns87415_reinit_one, |
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#endif |
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}; |
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module_pci_driver(ns87415_pci_driver); |
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MODULE_AUTHOR("Alan Cox"); |
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MODULE_DESCRIPTION("ATA low-level driver for NS87415 controllers"); |
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MODULE_LICENSE("GPL"); |
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MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl); |
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MODULE_VERSION(DRV_VERSION);
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