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301 lines
5.5 KiB
301 lines
5.5 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Intel Bay Trail Crystal Cove PMIC operation region driver |
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* |
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* Copyright (C) 2014 Intel Corporation. All rights reserved. |
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*/ |
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#include <linux/acpi.h> |
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#include <linux/init.h> |
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#include <linux/mfd/intel_soc_pmic.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include "intel_pmic.h" |
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#define PWR_SOURCE_SELECT BIT(1) |
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#define PMIC_A0LOCK_REG 0xc5 |
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static struct pmic_table power_table[] = { |
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/* { |
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.address = 0x00, |
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.reg = ??, |
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.bit = ??, |
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}, ** VSYS */ |
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{ |
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.address = 0x04, |
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.reg = 0x63, |
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.bit = 0x00, |
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}, /* SYSX -> VSYS_SX */ |
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{ |
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.address = 0x08, |
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.reg = 0x62, |
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.bit = 0x00, |
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}, /* SYSU -> VSYS_U */ |
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{ |
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.address = 0x0c, |
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.reg = 0x64, |
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.bit = 0x00, |
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}, /* SYSS -> VSYS_S */ |
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{ |
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.address = 0x10, |
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.reg = 0x6a, |
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.bit = 0x00, |
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}, /* V50S -> V5P0S */ |
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{ |
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.address = 0x14, |
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.reg = 0x6b, |
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.bit = 0x00, |
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}, /* HOST -> VHOST, USB2/3 host */ |
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{ |
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.address = 0x18, |
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.reg = 0x6c, |
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.bit = 0x00, |
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}, /* VBUS -> VBUS, USB2/3 OTG */ |
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{ |
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.address = 0x1c, |
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.reg = 0x6d, |
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.bit = 0x00, |
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}, /* HDMI -> VHDMI */ |
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/* { |
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.address = 0x20, |
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.reg = ??, |
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.bit = ??, |
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}, ** S285 */ |
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{ |
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.address = 0x24, |
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.reg = 0x66, |
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.bit = 0x00, |
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}, /* X285 -> V2P85SX, camera */ |
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/* { |
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.address = 0x28, |
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.reg = ??, |
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.bit = ??, |
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}, ** V33A */ |
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{ |
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.address = 0x2c, |
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.reg = 0x69, |
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.bit = 0x00, |
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}, /* V33S -> V3P3S, display/ssd/audio */ |
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{ |
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.address = 0x30, |
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.reg = 0x68, |
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.bit = 0x00, |
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}, /* V33U -> V3P3U, SDIO wifi&bt */ |
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/* { |
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.address = 0x34 .. 0x40, |
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.reg = ??, |
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.bit = ??, |
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}, ** V33I, V18A, REFQ, V12A */ |
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{ |
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.address = 0x44, |
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.reg = 0x5c, |
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.bit = 0x00, |
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}, /* V18S -> V1P8S, SOC/USB PHY/SIM */ |
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{ |
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.address = 0x48, |
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.reg = 0x5d, |
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.bit = 0x00, |
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}, /* V18X -> V1P8SX, eMMC/camara/audio */ |
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{ |
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.address = 0x4c, |
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.reg = 0x5b, |
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.bit = 0x00, |
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}, /* V18U -> V1P8U, LPDDR */ |
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{ |
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.address = 0x50, |
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.reg = 0x61, |
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.bit = 0x00, |
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}, /* V12X -> V1P2SX, SOC SFR */ |
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{ |
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.address = 0x54, |
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.reg = 0x60, |
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.bit = 0x00, |
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}, /* V12S -> V1P2S, MIPI */ |
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/* { |
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.address = 0x58, |
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.reg = ??, |
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.bit = ??, |
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}, ** V10A */ |
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{ |
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.address = 0x5c, |
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.reg = 0x56, |
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.bit = 0x00, |
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}, /* V10S -> V1P0S, SOC GFX */ |
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{ |
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.address = 0x60, |
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.reg = 0x57, |
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.bit = 0x00, |
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}, /* V10X -> V1P0SX, SOC display/DDR IO/PCIe */ |
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{ |
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.address = 0x64, |
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.reg = 0x59, |
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.bit = 0x00, |
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}, /* V105 -> V1P05S, L2 SRAM */ |
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}; |
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static struct pmic_table thermal_table[] = { |
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{ |
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.address = 0x00, |
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.reg = 0x75 |
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}, |
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{ |
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.address = 0x04, |
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.reg = 0x95 |
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}, |
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{ |
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.address = 0x08, |
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.reg = 0x97 |
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}, |
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{ |
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.address = 0x0c, |
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.reg = 0x77 |
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}, |
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{ |
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.address = 0x10, |
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.reg = 0x9a |
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}, |
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{ |
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.address = 0x14, |
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.reg = 0x9c |
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}, |
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{ |
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.address = 0x18, |
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.reg = 0x79 |
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}, |
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{ |
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.address = 0x1c, |
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.reg = 0x9f |
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}, |
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{ |
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.address = 0x20, |
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.reg = 0xa1 |
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}, |
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{ |
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.address = 0x48, |
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.reg = 0x94 |
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}, |
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{ |
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.address = 0x4c, |
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.reg = 0x99 |
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}, |
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{ |
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.address = 0x50, |
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.reg = 0x9e |
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}, |
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}; |
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static int intel_crc_pmic_get_power(struct regmap *regmap, int reg, |
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int bit, u64 *value) |
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{ |
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int data; |
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if (regmap_read(regmap, reg, &data)) |
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return -EIO; |
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*value = (data & PWR_SOURCE_SELECT) && (data & BIT(bit)) ? 1 : 0; |
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return 0; |
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} |
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static int intel_crc_pmic_update_power(struct regmap *regmap, int reg, |
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int bit, bool on) |
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{ |
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int data; |
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if (regmap_read(regmap, reg, &data)) |
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return -EIO; |
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if (on) { |
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data |= PWR_SOURCE_SELECT | BIT(bit); |
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} else { |
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data &= ~BIT(bit); |
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data |= PWR_SOURCE_SELECT; |
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} |
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if (regmap_write(regmap, reg, data)) |
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return -EIO; |
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return 0; |
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} |
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static int intel_crc_pmic_get_raw_temp(struct regmap *regmap, int reg) |
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{ |
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int temp_l, temp_h; |
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/* |
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* Raw temperature value is 10bits: 8bits in reg |
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* and 2bits in reg-1: bit0,1 |
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*/ |
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if (regmap_read(regmap, reg, &temp_l) || |
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regmap_read(regmap, reg - 1, &temp_h)) |
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return -EIO; |
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return temp_l | (temp_h & 0x3) << 8; |
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} |
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static int intel_crc_pmic_update_aux(struct regmap *regmap, int reg, int raw) |
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{ |
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return regmap_write(regmap, reg, raw) || |
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regmap_update_bits(regmap, reg - 1, 0x3, raw >> 8) ? -EIO : 0; |
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} |
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static int intel_crc_pmic_get_policy(struct regmap *regmap, |
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int reg, int bit, u64 *value) |
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{ |
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int pen; |
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if (regmap_read(regmap, reg, &pen)) |
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return -EIO; |
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*value = pen >> 7; |
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return 0; |
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} |
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static int intel_crc_pmic_update_policy(struct regmap *regmap, |
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int reg, int bit, int enable) |
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{ |
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int alert0; |
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/* Update to policy enable bit requires unlocking a0lock */ |
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if (regmap_read(regmap, PMIC_A0LOCK_REG, &alert0)) |
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return -EIO; |
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if (regmap_update_bits(regmap, PMIC_A0LOCK_REG, 0x01, 0)) |
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return -EIO; |
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if (regmap_update_bits(regmap, reg, 0x80, enable << 7)) |
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return -EIO; |
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/* restore alert0 */ |
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if (regmap_write(regmap, PMIC_A0LOCK_REG, alert0)) |
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return -EIO; |
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return 0; |
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} |
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static struct intel_pmic_opregion_data intel_crc_pmic_opregion_data = { |
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.get_power = intel_crc_pmic_get_power, |
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.update_power = intel_crc_pmic_update_power, |
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.get_raw_temp = intel_crc_pmic_get_raw_temp, |
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.update_aux = intel_crc_pmic_update_aux, |
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.get_policy = intel_crc_pmic_get_policy, |
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.update_policy = intel_crc_pmic_update_policy, |
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.power_table = power_table, |
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.power_table_count= ARRAY_SIZE(power_table), |
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.thermal_table = thermal_table, |
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.thermal_table_count = ARRAY_SIZE(thermal_table), |
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}; |
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static int intel_crc_pmic_opregion_probe(struct platform_device *pdev) |
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{ |
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struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent); |
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return intel_pmic_install_opregion_handler(&pdev->dev, |
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ACPI_HANDLE(pdev->dev.parent), pmic->regmap, |
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&intel_crc_pmic_opregion_data); |
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} |
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static struct platform_driver intel_crc_pmic_opregion_driver = { |
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.probe = intel_crc_pmic_opregion_probe, |
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.driver = { |
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.name = "byt_crystal_cove_pmic", |
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}, |
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}; |
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builtin_platform_driver(intel_crc_pmic_opregion_driver);
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