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90 lines
1.6 KiB
90 lines
1.6 KiB
/dts-v1/; |
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/ { |
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compatible = "andestech,ae3xx"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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interrupt-parent = <&intc>; |
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chosen { |
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stdout-path = &serial0; |
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}; |
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memory@0 { |
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device_type = "memory"; |
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reg = <0x00000000 0x40000000>; |
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}; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu@0 { |
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device_type = "cpu"; |
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compatible = "andestech,n13", "andestech,nds32v3"; |
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reg = <0>; |
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clock-frequency = <60000000>; |
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next-level-cache = <&L2>; |
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}; |
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}; |
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intc: interrupt-controller { |
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compatible = "andestech,ativic32"; |
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#interrupt-cells = <1>; |
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interrupt-controller; |
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}; |
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clock: clk { |
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#clock-cells = <0>; |
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compatible = "fixed-clock"; |
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clock-frequency = <30000000>; |
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}; |
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apb { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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serial0: serial@f0300000 { |
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compatible = "andestech,uart16550", "ns16550a"; |
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reg = <0xf0300000 0x1000>; |
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interrupts = <8>; |
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clock-frequency = <14745600>; |
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reg-shift = <2>; |
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reg-offset = <32>; |
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no-loopback-test = <1>; |
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}; |
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timer0: timer@f0400000 { |
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compatible = "andestech,atcpit100"; |
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reg = <0xf0400000 0x1000>; |
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interrupts = <2>; |
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clocks = <&clock>; |
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clock-names = "PCLK"; |
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}; |
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}; |
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ahb { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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L2: cache-controller@e0500000 { |
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compatible = "andestech,atl2c"; |
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reg = <0xe0500000 0x1000>; |
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cache-unified; |
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cache-level = <2>; |
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}; |
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mac0: ethernet@e0100000 { |
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compatible = "andestech,atmac100"; |
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reg = <0xe0100000 0x1000>; |
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interrupts = <18>; |
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}; |
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}; |
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pmu { |
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compatible = "andestech,nds32v3-pmu"; |
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interrupts= <13>; |
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}; |
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};
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