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764 lines
20 KiB
764 lines
20 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* An RTC driver for Allwinner A31/A23 |
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* |
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* Copyright (c) 2014, Chen-Yu Tsai <[email protected]> |
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* |
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* based on rtc-sunxi.c |
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* |
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* An RTC driver for Allwinner A10/A20 |
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* |
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* Copyright (c) 2013, Carlo Caione <[email protected]> |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/fs.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/rtc.h> |
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#include <linux/slab.h> |
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#include <linux/types.h> |
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/* Control register */ |
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#define SUN6I_LOSC_CTRL 0x0000 |
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#define SUN6I_LOSC_CTRL_KEY (0x16aa << 16) |
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#define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15) |
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#define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9) |
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#define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8) |
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#define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7) |
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#define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4) |
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#define SUN6I_LOSC_CTRL_EXT_OSC BIT(0) |
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#define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7) |
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|
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#define SUN6I_LOSC_CLK_PRESCAL 0x0008 |
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|
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/* RTC */ |
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#define SUN6I_RTC_YMD 0x0010 |
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#define SUN6I_RTC_HMS 0x0014 |
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|
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/* Alarm 0 (counter) */ |
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#define SUN6I_ALRM_COUNTER 0x0020 |
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#define SUN6I_ALRM_CUR_VAL 0x0024 |
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#define SUN6I_ALRM_EN 0x0028 |
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#define SUN6I_ALRM_EN_CNT_EN BIT(0) |
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#define SUN6I_ALRM_IRQ_EN 0x002c |
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#define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0) |
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#define SUN6I_ALRM_IRQ_STA 0x0030 |
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#define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0) |
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/* Alarm 1 (wall clock) */ |
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#define SUN6I_ALRM1_EN 0x0044 |
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#define SUN6I_ALRM1_IRQ_EN 0x0048 |
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#define SUN6I_ALRM1_IRQ_STA 0x004c |
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#define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0) |
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|
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/* Alarm config */ |
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#define SUN6I_ALARM_CONFIG 0x0050 |
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#define SUN6I_ALARM_CONFIG_WAKEUP BIT(0) |
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#define SUN6I_LOSC_OUT_GATING 0x0060 |
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#define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0 |
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|
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/* |
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* Get date values |
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*/ |
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#define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f) |
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#define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8) |
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#define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16) |
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#define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22) |
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|
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/* |
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* Get time values |
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*/ |
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#define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f) |
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#define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8) |
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#define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16) |
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/* |
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* Set date values |
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*/ |
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#define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f) |
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#define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00) |
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#define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000) |
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#define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000) |
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/* |
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* Set time values |
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*/ |
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#define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f) |
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#define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00) |
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#define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000) |
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|
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/* |
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* The year parameter passed to the driver is usually an offset relative to |
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* the year 1900. This macro is used to convert this offset to another one |
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* relative to the minimum year allowed by the hardware. |
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* |
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* The year range is 1970 - 2033. This range is selected to match Allwinner's |
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* driver, even though it is somewhat limited. |
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*/ |
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#define SUN6I_YEAR_MIN 1970 |
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#define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900) |
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|
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/* |
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* There are other differences between models, including: |
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* |
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* - number of GPIO pins that can be configured to hold a certain level |
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* - crypto-key related registers (H5, H6) |
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* - boot process related (super standby, secondary processor entry address) |
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* registers (R40, H6) |
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* - SYS power domain controls (R40) |
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* - DCXO controls (H6) |
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* - RC oscillator calibration (H6) |
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* |
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* These functions are not covered by this driver. |
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*/ |
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struct sun6i_rtc_clk_data { |
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unsigned long rc_osc_rate; |
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unsigned int fixed_prescaler : 16; |
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unsigned int has_prescaler : 1; |
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unsigned int has_out_clk : 1; |
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unsigned int export_iosc : 1; |
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unsigned int has_losc_en : 1; |
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unsigned int has_auto_swt : 1; |
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}; |
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struct sun6i_rtc_dev { |
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struct rtc_device *rtc; |
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const struct sun6i_rtc_clk_data *data; |
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void __iomem *base; |
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int irq; |
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unsigned long alarm; |
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struct clk_hw hw; |
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struct clk_hw *int_osc; |
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struct clk *losc; |
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struct clk *ext_losc; |
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spinlock_t lock; |
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}; |
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static struct sun6i_rtc_dev *sun6i_rtc; |
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static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); |
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u32 val = 0; |
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val = readl(rtc->base + SUN6I_LOSC_CTRL); |
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if (val & SUN6I_LOSC_CTRL_EXT_OSC) |
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return parent_rate; |
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if (rtc->data->fixed_prescaler) |
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parent_rate /= rtc->data->fixed_prescaler; |
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if (rtc->data->has_prescaler) { |
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val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL); |
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val &= GENMASK(4, 0); |
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} |
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return parent_rate / (val + 1); |
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} |
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static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw) |
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{ |
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struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); |
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return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC; |
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} |
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static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index) |
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{ |
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struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); |
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unsigned long flags; |
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u32 val; |
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if (index > 1) |
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return -EINVAL; |
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spin_lock_irqsave(&rtc->lock, flags); |
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val = readl(rtc->base + SUN6I_LOSC_CTRL); |
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val &= ~SUN6I_LOSC_CTRL_EXT_OSC; |
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val |= SUN6I_LOSC_CTRL_KEY; |
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val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0; |
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if (rtc->data->has_losc_en) { |
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val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN; |
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val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0; |
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} |
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writel(val, rtc->base + SUN6I_LOSC_CTRL); |
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spin_unlock_irqrestore(&rtc->lock, flags); |
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return 0; |
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} |
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static const struct clk_ops sun6i_rtc_osc_ops = { |
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.recalc_rate = sun6i_rtc_osc_recalc_rate, |
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|
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.get_parent = sun6i_rtc_osc_get_parent, |
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.set_parent = sun6i_rtc_osc_set_parent, |
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}; |
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static void __init sun6i_rtc_clk_init(struct device_node *node, |
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const struct sun6i_rtc_clk_data *data) |
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{ |
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struct clk_hw_onecell_data *clk_data; |
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struct sun6i_rtc_dev *rtc; |
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struct clk_init_data init = { |
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.ops = &sun6i_rtc_osc_ops, |
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.name = "losc", |
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}; |
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const char *iosc_name = "rtc-int-osc"; |
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const char *clkout_name = "osc32k-out"; |
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const char *parents[2]; |
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u32 reg; |
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rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); |
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if (!rtc) |
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return; |
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rtc->data = data; |
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clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL); |
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if (!clk_data) { |
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kfree(rtc); |
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return; |
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} |
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spin_lock_init(&rtc->lock); |
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rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node)); |
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if (IS_ERR(rtc->base)) { |
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pr_crit("Can't map RTC registers"); |
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goto err; |
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} |
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reg = SUN6I_LOSC_CTRL_KEY; |
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if (rtc->data->has_auto_swt) { |
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/* Bypass auto-switch to int osc, on ext losc failure */ |
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reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS; |
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writel(reg, rtc->base + SUN6I_LOSC_CTRL); |
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} |
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/* Switch to the external, more precise, oscillator, if present */ |
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if (of_get_property(node, "clocks", NULL)) { |
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reg |= SUN6I_LOSC_CTRL_EXT_OSC; |
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if (rtc->data->has_losc_en) |
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reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN; |
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} |
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writel(reg, rtc->base + SUN6I_LOSC_CTRL); |
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/* Yes, I know, this is ugly. */ |
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sun6i_rtc = rtc; |
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/* Only read IOSC name from device tree if it is exported */ |
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if (rtc->data->export_iosc) |
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of_property_read_string_index(node, "clock-output-names", 2, |
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&iosc_name); |
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rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL, |
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iosc_name, |
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NULL, 0, |
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rtc->data->rc_osc_rate, |
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300000000); |
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if (IS_ERR(rtc->int_osc)) { |
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pr_crit("Couldn't register the internal oscillator\n"); |
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goto err; |
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} |
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parents[0] = clk_hw_get_name(rtc->int_osc); |
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/* If there is no external oscillator, this will be NULL and ... */ |
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parents[1] = of_clk_get_parent_name(node, 0); |
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rtc->hw.init = &init; |
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init.parent_names = parents; |
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/* ... number of clock parents will be 1. */ |
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init.num_parents = of_clk_get_parent_count(node) + 1; |
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of_property_read_string_index(node, "clock-output-names", 0, |
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&init.name); |
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rtc->losc = clk_register(NULL, &rtc->hw); |
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if (IS_ERR(rtc->losc)) { |
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pr_crit("Couldn't register the LOSC clock\n"); |
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goto err_register; |
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} |
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of_property_read_string_index(node, "clock-output-names", 1, |
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&clkout_name); |
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rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name, |
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0, rtc->base + SUN6I_LOSC_OUT_GATING, |
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SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0, |
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&rtc->lock); |
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if (IS_ERR(rtc->ext_losc)) { |
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pr_crit("Couldn't register the LOSC external gate\n"); |
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goto err_register; |
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} |
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clk_data->num = 2; |
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clk_data->hws[0] = &rtc->hw; |
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clk_data->hws[1] = __clk_get_hw(rtc->ext_losc); |
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if (rtc->data->export_iosc) { |
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clk_data->hws[2] = rtc->int_osc; |
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clk_data->num = 3; |
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} |
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of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); |
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return; |
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|
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err_register: |
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clk_hw_unregister_fixed_rate(rtc->int_osc); |
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err: |
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kfree(clk_data); |
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} |
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static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = { |
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.rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ |
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.has_prescaler = 1, |
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}; |
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static void __init sun6i_a31_rtc_clk_init(struct device_node *node) |
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{ |
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sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data); |
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} |
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CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc", |
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sun6i_a31_rtc_clk_init); |
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static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = { |
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.rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ |
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.has_prescaler = 1, |
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.has_out_clk = 1, |
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}; |
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static void __init sun8i_a23_rtc_clk_init(struct device_node *node) |
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{ |
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sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data); |
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} |
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CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc", |
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sun8i_a23_rtc_clk_init); |
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static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = { |
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.rc_osc_rate = 16000000, |
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.fixed_prescaler = 32, |
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.has_prescaler = 1, |
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.has_out_clk = 1, |
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.export_iosc = 1, |
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}; |
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static void __init sun8i_h3_rtc_clk_init(struct device_node *node) |
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{ |
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sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data); |
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} |
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CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc", |
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sun8i_h3_rtc_clk_init); |
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/* As far as we are concerned, clocks for H5 are the same as H3 */ |
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CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc", |
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sun8i_h3_rtc_clk_init); |
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static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = { |
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.rc_osc_rate = 16000000, |
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.fixed_prescaler = 32, |
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.has_prescaler = 1, |
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.has_out_clk = 1, |
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.export_iosc = 1, |
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.has_losc_en = 1, |
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.has_auto_swt = 1, |
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}; |
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static void __init sun50i_h6_rtc_clk_init(struct device_node *node) |
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{ |
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sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data); |
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} |
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CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc", |
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sun50i_h6_rtc_clk_init); |
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|
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/* |
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* The R40 user manual is self-conflicting on whether the prescaler is |
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* fixed or configurable. The clock diagram shows it as fixed, but there |
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* is also a configurable divider in the RTC block. |
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*/ |
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static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = { |
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.rc_osc_rate = 16000000, |
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.fixed_prescaler = 512, |
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}; |
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static void __init sun8i_r40_rtc_clk_init(struct device_node *node) |
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{ |
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sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data); |
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} |
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CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc", |
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sun8i_r40_rtc_clk_init); |
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|
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static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = { |
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.rc_osc_rate = 32000, |
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.has_out_clk = 1, |
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}; |
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|
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static void __init sun8i_v3_rtc_clk_init(struct device_node *node) |
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{ |
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sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data); |
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} |
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CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc", |
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sun8i_v3_rtc_clk_init); |
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|
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static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id) |
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{ |
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struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id; |
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irqreturn_t ret = IRQ_NONE; |
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u32 val; |
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|
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spin_lock(&chip->lock); |
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val = readl(chip->base + SUN6I_ALRM_IRQ_STA); |
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|
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if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) { |
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val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND; |
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writel(val, chip->base + SUN6I_ALRM_IRQ_STA); |
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|
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rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF); |
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|
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ret = IRQ_HANDLED; |
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} |
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spin_unlock(&chip->lock); |
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|
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return ret; |
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} |
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|
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static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip) |
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{ |
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u32 alrm_val = 0; |
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u32 alrm_irq_val = 0; |
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u32 alrm_wake_val = 0; |
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unsigned long flags; |
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|
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if (to) { |
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alrm_val = SUN6I_ALRM_EN_CNT_EN; |
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alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN; |
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alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP; |
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} else { |
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writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, |
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chip->base + SUN6I_ALRM_IRQ_STA); |
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} |
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|
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spin_lock_irqsave(&chip->lock, flags); |
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writel(alrm_val, chip->base + SUN6I_ALRM_EN); |
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writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN); |
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writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG); |
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spin_unlock_irqrestore(&chip->lock, flags); |
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} |
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|
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static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) |
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{ |
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struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); |
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u32 date, time; |
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|
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/* |
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* read again in case it changes |
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*/ |
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do { |
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date = readl(chip->base + SUN6I_RTC_YMD); |
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time = readl(chip->base + SUN6I_RTC_HMS); |
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} while ((date != readl(chip->base + SUN6I_RTC_YMD)) || |
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(time != readl(chip->base + SUN6I_RTC_HMS))); |
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|
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rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time); |
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rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time); |
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rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time); |
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|
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rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date); |
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rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date); |
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rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date); |
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|
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rtc_tm->tm_mon -= 1; |
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|
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/* |
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* switch from (data_year->min)-relative offset to |
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* a (1900)-relative one |
|
*/ |
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rtc_tm->tm_year += SUN6I_YEAR_OFF; |
|
|
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return 0; |
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} |
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|
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static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm) |
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{ |
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struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); |
|
unsigned long flags; |
|
u32 alrm_st; |
|
u32 alrm_en; |
|
|
|
spin_lock_irqsave(&chip->lock, flags); |
|
alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN); |
|
alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA); |
|
spin_unlock_irqrestore(&chip->lock, flags); |
|
|
|
wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN); |
|
wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN); |
|
rtc_time64_to_tm(chip->alarm, &wkalrm->time); |
|
|
|
return 0; |
|
} |
|
|
|
static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm) |
|
{ |
|
struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); |
|
struct rtc_time *alrm_tm = &wkalrm->time; |
|
struct rtc_time tm_now; |
|
unsigned long time_now = 0; |
|
unsigned long time_set = 0; |
|
unsigned long time_gap = 0; |
|
int ret = 0; |
|
|
|
ret = sun6i_rtc_gettime(dev, &tm_now); |
|
if (ret < 0) { |
|
dev_err(dev, "Error in getting time\n"); |
|
return -EINVAL; |
|
} |
|
|
|
time_set = rtc_tm_to_time64(alrm_tm); |
|
time_now = rtc_tm_to_time64(&tm_now); |
|
if (time_set <= time_now) { |
|
dev_err(dev, "Date to set in the past\n"); |
|
return -EINVAL; |
|
} |
|
|
|
time_gap = time_set - time_now; |
|
|
|
if (time_gap > U32_MAX) { |
|
dev_err(dev, "Date too far in the future\n"); |
|
return -EINVAL; |
|
} |
|
|
|
sun6i_rtc_setaie(0, chip); |
|
writel(0, chip->base + SUN6I_ALRM_COUNTER); |
|
usleep_range(100, 300); |
|
|
|
writel(time_gap, chip->base + SUN6I_ALRM_COUNTER); |
|
chip->alarm = time_set; |
|
|
|
sun6i_rtc_setaie(wkalrm->enabled, chip); |
|
|
|
return 0; |
|
} |
|
|
|
static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset, |
|
unsigned int mask, unsigned int ms_timeout) |
|
{ |
|
const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout); |
|
u32 reg; |
|
|
|
do { |
|
reg = readl(chip->base + offset); |
|
reg &= mask; |
|
|
|
if (!reg) |
|
return 0; |
|
|
|
} while (time_before(jiffies, timeout)); |
|
|
|
return -ETIMEDOUT; |
|
} |
|
|
|
static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm) |
|
{ |
|
struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); |
|
u32 date = 0; |
|
u32 time = 0; |
|
|
|
rtc_tm->tm_year -= SUN6I_YEAR_OFF; |
|
rtc_tm->tm_mon += 1; |
|
|
|
date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) | |
|
SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) | |
|
SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year); |
|
|
|
if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN)) |
|
date |= SUN6I_LEAP_SET_VALUE(1); |
|
|
|
time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) | |
|
SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) | |
|
SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour); |
|
|
|
/* Check whether registers are writable */ |
|
if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, |
|
SUN6I_LOSC_CTRL_ACC_MASK, 50)) { |
|
dev_err(dev, "rtc is still busy.\n"); |
|
return -EBUSY; |
|
} |
|
|
|
writel(time, chip->base + SUN6I_RTC_HMS); |
|
|
|
/* |
|
* After writing the RTC HH-MM-SS register, the |
|
* SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not |
|
* be cleared until the real writing operation is finished |
|
*/ |
|
|
|
if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, |
|
SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) { |
|
dev_err(dev, "Failed to set rtc time.\n"); |
|
return -ETIMEDOUT; |
|
} |
|
|
|
writel(date, chip->base + SUN6I_RTC_YMD); |
|
|
|
/* |
|
* After writing the RTC YY-MM-DD register, the |
|
* SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not |
|
* be cleared until the real writing operation is finished |
|
*/ |
|
|
|
if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, |
|
SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) { |
|
dev_err(dev, "Failed to set rtc time.\n"); |
|
return -ETIMEDOUT; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
|
{ |
|
struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); |
|
|
|
if (!enabled) |
|
sun6i_rtc_setaie(enabled, chip); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct rtc_class_ops sun6i_rtc_ops = { |
|
.read_time = sun6i_rtc_gettime, |
|
.set_time = sun6i_rtc_settime, |
|
.read_alarm = sun6i_rtc_getalarm, |
|
.set_alarm = sun6i_rtc_setalarm, |
|
.alarm_irq_enable = sun6i_rtc_alarm_irq_enable |
|
}; |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
/* Enable IRQ wake on suspend, to wake up from RTC. */ |
|
static int sun6i_rtc_suspend(struct device *dev) |
|
{ |
|
struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); |
|
|
|
if (device_may_wakeup(dev)) |
|
enable_irq_wake(chip->irq); |
|
|
|
return 0; |
|
} |
|
|
|
/* Disable IRQ wake on resume. */ |
|
static int sun6i_rtc_resume(struct device *dev) |
|
{ |
|
struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); |
|
|
|
if (device_may_wakeup(dev)) |
|
disable_irq_wake(chip->irq); |
|
|
|
return 0; |
|
} |
|
#endif |
|
|
|
static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops, |
|
sun6i_rtc_suspend, sun6i_rtc_resume); |
|
|
|
static int sun6i_rtc_probe(struct platform_device *pdev) |
|
{ |
|
struct sun6i_rtc_dev *chip = sun6i_rtc; |
|
int ret; |
|
|
|
if (!chip) |
|
return -ENODEV; |
|
|
|
platform_set_drvdata(pdev, chip); |
|
|
|
chip->irq = platform_get_irq(pdev, 0); |
|
if (chip->irq < 0) |
|
return chip->irq; |
|
|
|
ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq, |
|
0, dev_name(&pdev->dev), chip); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Could not request IRQ\n"); |
|
return ret; |
|
} |
|
|
|
/* clear the alarm counter value */ |
|
writel(0, chip->base + SUN6I_ALRM_COUNTER); |
|
|
|
/* disable counter alarm */ |
|
writel(0, chip->base + SUN6I_ALRM_EN); |
|
|
|
/* disable counter alarm interrupt */ |
|
writel(0, chip->base + SUN6I_ALRM_IRQ_EN); |
|
|
|
/* disable week alarm */ |
|
writel(0, chip->base + SUN6I_ALRM1_EN); |
|
|
|
/* disable week alarm interrupt */ |
|
writel(0, chip->base + SUN6I_ALRM1_IRQ_EN); |
|
|
|
/* clear counter alarm pending interrupts */ |
|
writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, |
|
chip->base + SUN6I_ALRM_IRQ_STA); |
|
|
|
/* clear week alarm pending interrupts */ |
|
writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND, |
|
chip->base + SUN6I_ALRM1_IRQ_STA); |
|
|
|
/* disable alarm wakeup */ |
|
writel(0, chip->base + SUN6I_ALARM_CONFIG); |
|
|
|
clk_prepare_enable(chip->losc); |
|
|
|
device_init_wakeup(&pdev->dev, 1); |
|
|
|
chip->rtc = devm_rtc_allocate_device(&pdev->dev); |
|
if (IS_ERR(chip->rtc)) |
|
return PTR_ERR(chip->rtc); |
|
|
|
chip->rtc->ops = &sun6i_rtc_ops; |
|
chip->rtc->range_max = 2019686399LL; /* 2033-12-31 23:59:59 */ |
|
|
|
ret = devm_rtc_register_device(chip->rtc); |
|
if (ret) |
|
return ret; |
|
|
|
dev_info(&pdev->dev, "RTC enabled\n"); |
|
|
|
return 0; |
|
} |
|
|
|
/* |
|
* As far as RTC functionality goes, all models are the same. The |
|
* datasheets claim that different models have different number of |
|
* registers available for non-volatile storage, but experiments show |
|
* that all SoCs have 16 registers available for this purpose. |
|
*/ |
|
static const struct of_device_id sun6i_rtc_dt_ids[] = { |
|
{ .compatible = "allwinner,sun6i-a31-rtc" }, |
|
{ .compatible = "allwinner,sun8i-a23-rtc" }, |
|
{ .compatible = "allwinner,sun8i-h3-rtc" }, |
|
{ .compatible = "allwinner,sun8i-r40-rtc" }, |
|
{ .compatible = "allwinner,sun8i-v3-rtc" }, |
|
{ .compatible = "allwinner,sun50i-h5-rtc" }, |
|
{ .compatible = "allwinner,sun50i-h6-rtc" }, |
|
{ /* sentinel */ }, |
|
}; |
|
MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); |
|
|
|
static struct platform_driver sun6i_rtc_driver = { |
|
.probe = sun6i_rtc_probe, |
|
.driver = { |
|
.name = "sun6i-rtc", |
|
.of_match_table = sun6i_rtc_dt_ids, |
|
.pm = &sun6i_rtc_pm_ops, |
|
}, |
|
}; |
|
builtin_platform_driver(sun6i_rtc_driver);
|
|
|