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716 lines
23 KiB
716 lines
23 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef DRIVERS_PCI_H |
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#define DRIVERS_PCI_H |
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#include <linux/pci.h> |
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/* Number of possible devfns: 0.0 to 1f.7 inclusive */ |
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#define MAX_NR_DEVFNS 256 |
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#define PCI_FIND_CAP_TTL 48 |
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#define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ |
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extern const unsigned char pcie_link_speed[]; |
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extern bool pci_early_dump; |
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bool pcie_cap_has_lnkctl(const struct pci_dev *dev); |
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bool pcie_cap_has_rtctl(const struct pci_dev *dev); |
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/* Functions internal to the PCI core code */ |
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int pci_create_sysfs_dev_files(struct pci_dev *pdev); |
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void pci_remove_sysfs_dev_files(struct pci_dev *pdev); |
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#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI) |
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static inline void pci_create_firmware_label_files(struct pci_dev *pdev) |
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{ return; } |
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static inline void pci_remove_firmware_label_files(struct pci_dev *pdev) |
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{ return; } |
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#else |
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void pci_create_firmware_label_files(struct pci_dev *pdev); |
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void pci_remove_firmware_label_files(struct pci_dev *pdev); |
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#endif |
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void pci_cleanup_rom(struct pci_dev *dev); |
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enum pci_mmap_api { |
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PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ |
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PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ |
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}; |
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int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, |
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enum pci_mmap_api mmap_api); |
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int pci_probe_reset_function(struct pci_dev *dev); |
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int pci_bridge_secondary_bus_reset(struct pci_dev *dev); |
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int pci_bus_error_reset(struct pci_dev *dev); |
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#define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ |
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#define PCI_PM_D3HOT_WAIT 10 /* msec */ |
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#define PCI_PM_D3COLD_WAIT 100 /* msec */ |
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/** |
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* struct pci_platform_pm_ops - Firmware PM callbacks |
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* |
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* @bridge_d3: Does the bridge allow entering into D3 |
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* |
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* @is_manageable: returns 'true' if given device is power manageable by the |
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* platform firmware |
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* |
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* @set_state: invokes the platform firmware to set the device's power state |
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* |
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* @get_state: queries the platform firmware for a device's current power state |
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* |
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* @refresh_state: asks the platform to refresh the device's power state data |
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* |
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* @choose_state: returns PCI power state of given device preferred by the |
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* platform; to be used during system-wide transitions from a |
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* sleeping state to the working state and vice versa |
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* |
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* @set_wakeup: enables/disables wakeup capability for the device |
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* |
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* @need_resume: returns 'true' if the given device (which is currently |
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* suspended) needs to be resumed to be configured for system |
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* wakeup. |
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* |
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* If given platform is generally capable of power managing PCI devices, all of |
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* these callbacks are mandatory. |
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*/ |
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struct pci_platform_pm_ops { |
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bool (*bridge_d3)(struct pci_dev *dev); |
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bool (*is_manageable)(struct pci_dev *dev); |
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int (*set_state)(struct pci_dev *dev, pci_power_t state); |
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pci_power_t (*get_state)(struct pci_dev *dev); |
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void (*refresh_state)(struct pci_dev *dev); |
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pci_power_t (*choose_state)(struct pci_dev *dev); |
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int (*set_wakeup)(struct pci_dev *dev, bool enable); |
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bool (*need_resume)(struct pci_dev *dev); |
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}; |
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int pci_set_platform_pm(const struct pci_platform_pm_ops *ops); |
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void pci_update_current_state(struct pci_dev *dev, pci_power_t state); |
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void pci_refresh_power_state(struct pci_dev *dev); |
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int pci_power_up(struct pci_dev *dev); |
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void pci_disable_enabled_device(struct pci_dev *dev); |
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int pci_finish_runtime_suspend(struct pci_dev *dev); |
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void pcie_clear_device_status(struct pci_dev *dev); |
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void pcie_clear_root_pme_status(struct pci_dev *dev); |
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bool pci_check_pme_status(struct pci_dev *dev); |
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void pci_pme_wakeup_bus(struct pci_bus *bus); |
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int __pci_pme_wakeup(struct pci_dev *dev, void *ign); |
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void pci_pme_restore(struct pci_dev *dev); |
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bool pci_dev_need_resume(struct pci_dev *dev); |
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void pci_dev_adjust_pme(struct pci_dev *dev); |
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void pci_dev_complete_resume(struct pci_dev *pci_dev); |
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void pci_config_pm_runtime_get(struct pci_dev *dev); |
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void pci_config_pm_runtime_put(struct pci_dev *dev); |
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void pci_pm_init(struct pci_dev *dev); |
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void pci_ea_init(struct pci_dev *dev); |
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void pci_msi_init(struct pci_dev *dev); |
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void pci_msix_init(struct pci_dev *dev); |
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void pci_allocate_cap_save_buffers(struct pci_dev *dev); |
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void pci_free_cap_save_buffers(struct pci_dev *dev); |
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bool pci_bridge_d3_possible(struct pci_dev *dev); |
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void pci_bridge_d3_update(struct pci_dev *dev); |
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void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev); |
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static inline void pci_wakeup_event(struct pci_dev *dev) |
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{ |
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/* Wait 100 ms before the system can be put into a sleep state. */ |
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pm_wakeup_event(&dev->dev, 100); |
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} |
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static inline bool pci_has_subordinate(struct pci_dev *pci_dev) |
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{ |
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return !!(pci_dev->subordinate); |
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} |
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static inline bool pci_power_manageable(struct pci_dev *pci_dev) |
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{ |
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/* |
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* Currently we allow normal PCI devices and PCI bridges transition |
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* into D3 if their bridge_d3 is set. |
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*/ |
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return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; |
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} |
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static inline bool pcie_downstream_port(const struct pci_dev *dev) |
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{ |
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int type = pci_pcie_type(dev); |
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return type == PCI_EXP_TYPE_ROOT_PORT || |
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type == PCI_EXP_TYPE_DOWNSTREAM || |
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type == PCI_EXP_TYPE_PCIE_BRIDGE; |
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} |
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int pci_vpd_init(struct pci_dev *dev); |
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void pci_vpd_release(struct pci_dev *dev); |
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void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev); |
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void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev); |
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/* PCI Virtual Channel */ |
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int pci_save_vc_state(struct pci_dev *dev); |
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void pci_restore_vc_state(struct pci_dev *dev); |
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void pci_allocate_vc_save_buffers(struct pci_dev *dev); |
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/* PCI /proc functions */ |
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#ifdef CONFIG_PROC_FS |
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int pci_proc_attach_device(struct pci_dev *dev); |
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int pci_proc_detach_device(struct pci_dev *dev); |
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int pci_proc_detach_bus(struct pci_bus *bus); |
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#else |
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static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } |
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static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } |
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static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } |
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#endif |
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/* Functions for PCI Hotplug drivers to use */ |
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int pci_hp_add_bridge(struct pci_dev *dev); |
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#ifdef HAVE_PCI_LEGACY |
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void pci_create_legacy_files(struct pci_bus *bus); |
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void pci_remove_legacy_files(struct pci_bus *bus); |
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#else |
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static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } |
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static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } |
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#endif |
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/* Lock for read/write access to pci device and bus lists */ |
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extern struct rw_semaphore pci_bus_sem; |
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extern struct mutex pci_slot_mutex; |
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extern raw_spinlock_t pci_lock; |
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extern unsigned int pci_pm_d3hot_delay; |
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#ifdef CONFIG_PCI_MSI |
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void pci_no_msi(void); |
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#else |
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static inline void pci_no_msi(void) { } |
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#endif |
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void pci_realloc_get_opt(char *); |
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static inline int pci_no_d1d2(struct pci_dev *dev) |
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{ |
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unsigned int parent_dstates = 0; |
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if (dev->bus->self) |
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parent_dstates = dev->bus->self->no_d1d2; |
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return (dev->no_d1d2 || parent_dstates); |
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} |
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extern const struct attribute_group *pci_dev_groups[]; |
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extern const struct attribute_group *pcibus_groups[]; |
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extern const struct device_type pci_dev_type; |
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extern const struct attribute_group *pci_bus_groups[]; |
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extern unsigned long pci_hotplug_io_size; |
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extern unsigned long pci_hotplug_mmio_size; |
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extern unsigned long pci_hotplug_mmio_pref_size; |
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extern unsigned long pci_hotplug_bus_size; |
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/** |
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* pci_match_one_device - Tell if a PCI device structure has a matching |
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* PCI device id structure |
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* @id: single PCI device id structure to match |
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* @dev: the PCI device structure to match against |
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* |
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* Returns the matching pci_device_id structure or %NULL if there is no match. |
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*/ |
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static inline const struct pci_device_id * |
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pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) |
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{ |
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if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && |
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(id->device == PCI_ANY_ID || id->device == dev->device) && |
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(id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && |
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(id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && |
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!((id->class ^ dev->class) & id->class_mask)) |
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return id; |
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return NULL; |
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} |
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/* PCI slot sysfs helper code */ |
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#define to_pci_slot(s) container_of(s, struct pci_slot, kobj) |
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extern struct kset *pci_slots_kset; |
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struct pci_slot_attribute { |
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struct attribute attr; |
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ssize_t (*show)(struct pci_slot *, char *); |
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ssize_t (*store)(struct pci_slot *, const char *, size_t); |
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}; |
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#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) |
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enum pci_bar_type { |
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pci_bar_unknown, /* Standard PCI BAR probe */ |
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pci_bar_io, /* An I/O port BAR */ |
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pci_bar_mem32, /* A 32-bit memory BAR */ |
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pci_bar_mem64, /* A 64-bit memory BAR */ |
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}; |
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struct device *pci_get_host_bridge_device(struct pci_dev *dev); |
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void pci_put_host_bridge_device(struct device *dev); |
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int pci_configure_extended_tags(struct pci_dev *dev, void *ign); |
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bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, |
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int crs_timeout); |
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bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, |
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int crs_timeout); |
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int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); |
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int pci_setup_device(struct pci_dev *dev); |
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int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
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struct resource *res, unsigned int reg); |
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void pci_configure_ari(struct pci_dev *dev); |
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void __pci_bus_size_bridges(struct pci_bus *bus, |
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struct list_head *realloc_head); |
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void __pci_bus_assign_resources(const struct pci_bus *bus, |
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struct list_head *realloc_head, |
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struct list_head *fail_head); |
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bool pci_bus_clip_resource(struct pci_dev *dev, int idx); |
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void pci_reassigndev_resource_alignment(struct pci_dev *dev); |
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void pci_disable_bridge_window(struct pci_dev *dev); |
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struct pci_bus *pci_bus_get(struct pci_bus *bus); |
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void pci_bus_put(struct pci_bus *bus); |
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/* PCIe link information from Link Capabilities 2 */ |
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#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ |
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((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ |
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(lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ |
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(lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ |
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(lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ |
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(lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ |
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(lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ |
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PCI_SPEED_UNKNOWN) |
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/* PCIe speed to Mb/s reduced by encoding overhead */ |
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#define PCIE_SPEED2MBS_ENC(speed) \ |
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((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \ |
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(speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ |
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(speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ |
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(speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ |
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(speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ |
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(speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ |
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0) |
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const char *pci_speed_string(enum pci_bus_speed speed); |
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enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); |
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enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); |
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u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, |
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enum pcie_link_width *width); |
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void __pcie_print_link_status(struct pci_dev *dev, bool verbose); |
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void pcie_report_downtraining(struct pci_dev *dev); |
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void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); |
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/* Single Root I/O Virtualization */ |
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struct pci_sriov { |
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int pos; /* Capability position */ |
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int nres; /* Number of resources */ |
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u32 cap; /* SR-IOV Capabilities */ |
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u16 ctrl; /* SR-IOV Control */ |
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u16 total_VFs; /* Total VFs associated with the PF */ |
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u16 initial_VFs; /* Initial VFs associated with the PF */ |
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u16 num_VFs; /* Number of VFs available */ |
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u16 offset; /* First VF Routing ID offset */ |
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u16 stride; /* Following VF stride */ |
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u16 vf_device; /* VF device ID */ |
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u32 pgsz; /* Page size for BAR alignment */ |
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u8 link; /* Function Dependency Link */ |
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u8 max_VF_buses; /* Max buses consumed by VFs */ |
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u16 driver_max_VFs; /* Max num VFs driver supports */ |
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struct pci_dev *dev; /* Lowest numbered PF */ |
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struct pci_dev *self; /* This PF */ |
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u32 class; /* VF device */ |
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u8 hdr_type; /* VF header type */ |
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u16 subsystem_vendor; /* VF subsystem vendor */ |
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u16 subsystem_device; /* VF subsystem device */ |
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resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ |
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bool drivers_autoprobe; /* Auto probing of VFs by driver */ |
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}; |
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/** |
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* pci_dev_set_io_state - Set the new error state if possible. |
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* |
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* @dev - pci device to set new error_state |
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* @new - the state we want dev to be in |
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* |
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* Must be called with device_lock held. |
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* |
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* Returns true if state has been changed to the requested state. |
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*/ |
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static inline bool pci_dev_set_io_state(struct pci_dev *dev, |
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pci_channel_state_t new) |
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{ |
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bool changed = false; |
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device_lock_assert(&dev->dev); |
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switch (new) { |
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case pci_channel_io_perm_failure: |
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switch (dev->error_state) { |
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case pci_channel_io_frozen: |
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case pci_channel_io_normal: |
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case pci_channel_io_perm_failure: |
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changed = true; |
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break; |
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} |
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break; |
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case pci_channel_io_frozen: |
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switch (dev->error_state) { |
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case pci_channel_io_frozen: |
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case pci_channel_io_normal: |
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changed = true; |
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break; |
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} |
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break; |
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case pci_channel_io_normal: |
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switch (dev->error_state) { |
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case pci_channel_io_frozen: |
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case pci_channel_io_normal: |
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changed = true; |
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break; |
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} |
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break; |
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} |
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if (changed) |
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dev->error_state = new; |
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return changed; |
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} |
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static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) |
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{ |
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device_lock(&dev->dev); |
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pci_dev_set_io_state(dev, pci_channel_io_perm_failure); |
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device_unlock(&dev->dev); |
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return 0; |
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} |
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static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) |
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{ |
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return dev->error_state == pci_channel_io_perm_failure; |
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} |
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/* pci_dev priv_flags */ |
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#define PCI_DEV_ADDED 0 |
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static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) |
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{ |
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assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); |
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} |
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static inline bool pci_dev_is_added(const struct pci_dev *dev) |
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{ |
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return test_bit(PCI_DEV_ADDED, &dev->priv_flags); |
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} |
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#ifdef CONFIG_PCIEAER |
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#include <linux/aer.h> |
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#define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ |
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struct aer_err_info { |
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struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; |
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int error_dev_num; |
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unsigned int id:16; |
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unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ |
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unsigned int __pad1:5; |
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unsigned int multi_error_valid:1; |
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unsigned int first_error:5; |
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unsigned int __pad2:2; |
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unsigned int tlp_header_valid:1; |
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unsigned int status; /* COR/UNCOR Error Status */ |
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unsigned int mask; /* COR/UNCOR Error Mask */ |
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struct aer_header_log_regs tlp; /* TLP Header */ |
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}; |
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int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); |
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void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); |
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#endif /* CONFIG_PCIEAER */ |
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#ifdef CONFIG_PCIEPORTBUS |
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/* Cached RCEC Endpoint Association */ |
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struct rcec_ea { |
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u8 nextbusn; |
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u8 lastbusn; |
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u32 bitmap; |
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}; |
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#endif |
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#ifdef CONFIG_PCIE_DPC |
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void pci_save_dpc_state(struct pci_dev *dev); |
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void pci_restore_dpc_state(struct pci_dev *dev); |
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void pci_dpc_init(struct pci_dev *pdev); |
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void dpc_process_error(struct pci_dev *pdev); |
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pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); |
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#else |
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static inline void pci_save_dpc_state(struct pci_dev *dev) {} |
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static inline void pci_restore_dpc_state(struct pci_dev *dev) {} |
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static inline void pci_dpc_init(struct pci_dev *pdev) {} |
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#endif |
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#ifdef CONFIG_PCIEPORTBUS |
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void pci_rcec_init(struct pci_dev *dev); |
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void pci_rcec_exit(struct pci_dev *dev); |
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void pcie_link_rcec(struct pci_dev *rcec); |
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void pcie_walk_rcec(struct pci_dev *rcec, |
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int (*cb)(struct pci_dev *, void *), |
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void *userdata); |
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#else |
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static inline void pci_rcec_init(struct pci_dev *dev) {} |
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static inline void pci_rcec_exit(struct pci_dev *dev) {} |
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static inline void pcie_link_rcec(struct pci_dev *rcec) {} |
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static inline void pcie_walk_rcec(struct pci_dev *rcec, |
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int (*cb)(struct pci_dev *, void *), |
|
void *userdata) {} |
|
#endif |
|
|
|
#ifdef CONFIG_PCI_ATS |
|
/* Address Translation Service */ |
|
void pci_ats_init(struct pci_dev *dev); |
|
void pci_restore_ats_state(struct pci_dev *dev); |
|
#else |
|
static inline void pci_ats_init(struct pci_dev *d) { } |
|
static inline void pci_restore_ats_state(struct pci_dev *dev) { } |
|
#endif /* CONFIG_PCI_ATS */ |
|
|
|
#ifdef CONFIG_PCI_PRI |
|
void pci_pri_init(struct pci_dev *dev); |
|
void pci_restore_pri_state(struct pci_dev *pdev); |
|
#else |
|
static inline void pci_pri_init(struct pci_dev *dev) { } |
|
static inline void pci_restore_pri_state(struct pci_dev *pdev) { } |
|
#endif |
|
|
|
#ifdef CONFIG_PCI_PASID |
|
void pci_pasid_init(struct pci_dev *dev); |
|
void pci_restore_pasid_state(struct pci_dev *pdev); |
|
#else |
|
static inline void pci_pasid_init(struct pci_dev *dev) { } |
|
static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } |
|
#endif |
|
|
|
#ifdef CONFIG_PCI_IOV |
|
int pci_iov_init(struct pci_dev *dev); |
|
void pci_iov_release(struct pci_dev *dev); |
|
void pci_iov_remove(struct pci_dev *dev); |
|
void pci_iov_update_resource(struct pci_dev *dev, int resno); |
|
resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); |
|
void pci_restore_iov_state(struct pci_dev *dev); |
|
int pci_iov_bus_range(struct pci_bus *bus); |
|
extern const struct attribute_group sriov_dev_attr_group; |
|
#else |
|
static inline int pci_iov_init(struct pci_dev *dev) |
|
{ |
|
return -ENODEV; |
|
} |
|
static inline void pci_iov_release(struct pci_dev *dev) |
|
|
|
{ |
|
} |
|
static inline void pci_iov_remove(struct pci_dev *dev) |
|
{ |
|
} |
|
static inline void pci_restore_iov_state(struct pci_dev *dev) |
|
{ |
|
} |
|
static inline int pci_iov_bus_range(struct pci_bus *bus) |
|
{ |
|
return 0; |
|
} |
|
|
|
#endif /* CONFIG_PCI_IOV */ |
|
|
|
#ifdef CONFIG_PCIE_PTM |
|
void pci_save_ptm_state(struct pci_dev *dev); |
|
void pci_restore_ptm_state(struct pci_dev *dev); |
|
void pci_disable_ptm(struct pci_dev *dev); |
|
#else |
|
static inline void pci_save_ptm_state(struct pci_dev *dev) { } |
|
static inline void pci_restore_ptm_state(struct pci_dev *dev) { } |
|
static inline void pci_disable_ptm(struct pci_dev *dev) { } |
|
#endif |
|
|
|
unsigned long pci_cardbus_resource_alignment(struct resource *); |
|
|
|
static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, |
|
struct resource *res) |
|
{ |
|
#ifdef CONFIG_PCI_IOV |
|
int resno = res - dev->resource; |
|
|
|
if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) |
|
return pci_sriov_resource_alignment(dev, resno); |
|
#endif |
|
if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) |
|
return pci_cardbus_resource_alignment(res); |
|
return resource_alignment(res); |
|
} |
|
|
|
void pci_acs_init(struct pci_dev *dev); |
|
#ifdef CONFIG_PCI_QUIRKS |
|
int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); |
|
int pci_dev_specific_enable_acs(struct pci_dev *dev); |
|
int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); |
|
#else |
|
static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, |
|
u16 acs_flags) |
|
{ |
|
return -ENOTTY; |
|
} |
|
static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) |
|
{ |
|
return -ENOTTY; |
|
} |
|
static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) |
|
{ |
|
return -ENOTTY; |
|
} |
|
#endif |
|
|
|
/* PCI error reporting and recovery */ |
|
pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, |
|
pci_channel_state_t state, |
|
pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); |
|
|
|
bool pcie_wait_for_link(struct pci_dev *pdev, bool active); |
|
#ifdef CONFIG_PCIEASPM |
|
void pcie_aspm_init_link_state(struct pci_dev *pdev); |
|
void pcie_aspm_exit_link_state(struct pci_dev *pdev); |
|
void pcie_aspm_pm_state_change(struct pci_dev *pdev); |
|
void pcie_aspm_powersave_config_link(struct pci_dev *pdev); |
|
#else |
|
static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } |
|
static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } |
|
static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { } |
|
static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } |
|
#endif |
|
|
|
#ifdef CONFIG_PCIE_ECRC |
|
void pcie_set_ecrc_checking(struct pci_dev *dev); |
|
void pcie_ecrc_get_policy(char *str); |
|
#else |
|
static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } |
|
static inline void pcie_ecrc_get_policy(char *str) { } |
|
#endif |
|
|
|
#ifdef CONFIG_PCIE_PTM |
|
void pci_ptm_init(struct pci_dev *dev); |
|
int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); |
|
#else |
|
static inline void pci_ptm_init(struct pci_dev *dev) { } |
|
static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) |
|
{ return -EINVAL; } |
|
#endif |
|
|
|
struct pci_dev_reset_methods { |
|
u16 vendor; |
|
u16 device; |
|
int (*reset)(struct pci_dev *dev, int probe); |
|
}; |
|
|
|
#ifdef CONFIG_PCI_QUIRKS |
|
int pci_dev_specific_reset(struct pci_dev *dev, int probe); |
|
#else |
|
static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) |
|
{ |
|
return -ENOTTY; |
|
} |
|
#endif |
|
|
|
#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) |
|
int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, |
|
struct resource *res); |
|
#else |
|
static inline int acpi_get_rc_resources(struct device *dev, const char *hid, |
|
u16 segment, struct resource *res) |
|
{ |
|
return -ENODEV; |
|
} |
|
#endif |
|
|
|
int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); |
|
int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); |
|
static inline u64 pci_rebar_size_to_bytes(int size) |
|
{ |
|
return 1ULL << (size + 20); |
|
} |
|
|
|
struct device_node; |
|
|
|
#ifdef CONFIG_OF |
|
int of_pci_parse_bus_range(struct device_node *node, struct resource *res); |
|
int of_get_pci_domain_nr(struct device_node *node); |
|
int of_pci_get_max_link_speed(struct device_node *node); |
|
void pci_set_of_node(struct pci_dev *dev); |
|
void pci_release_of_node(struct pci_dev *dev); |
|
void pci_set_bus_of_node(struct pci_bus *bus); |
|
void pci_release_bus_of_node(struct pci_bus *bus); |
|
|
|
int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); |
|
|
|
#else |
|
static inline int |
|
of_pci_parse_bus_range(struct device_node *node, struct resource *res) |
|
{ |
|
return -EINVAL; |
|
} |
|
|
|
static inline int |
|
of_get_pci_domain_nr(struct device_node *node) |
|
{ |
|
return -1; |
|
} |
|
|
|
static inline int |
|
of_pci_get_max_link_speed(struct device_node *node) |
|
{ |
|
return -EINVAL; |
|
} |
|
|
|
static inline void pci_set_of_node(struct pci_dev *dev) { } |
|
static inline void pci_release_of_node(struct pci_dev *dev) { } |
|
static inline void pci_set_bus_of_node(struct pci_bus *bus) { } |
|
static inline void pci_release_bus_of_node(struct pci_bus *bus) { } |
|
|
|
static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) |
|
{ |
|
return 0; |
|
} |
|
|
|
#endif /* CONFIG_OF */ |
|
|
|
#ifdef CONFIG_PCIEAER |
|
void pci_no_aer(void); |
|
void pci_aer_init(struct pci_dev *dev); |
|
void pci_aer_exit(struct pci_dev *dev); |
|
extern const struct attribute_group aer_stats_attr_group; |
|
void pci_aer_clear_fatal_status(struct pci_dev *dev); |
|
int pci_aer_clear_status(struct pci_dev *dev); |
|
int pci_aer_raw_clear_status(struct pci_dev *dev); |
|
#else |
|
static inline void pci_no_aer(void) { } |
|
static inline void pci_aer_init(struct pci_dev *d) { } |
|
static inline void pci_aer_exit(struct pci_dev *d) { } |
|
static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } |
|
static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } |
|
static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } |
|
#endif |
|
|
|
#ifdef CONFIG_ACPI |
|
int pci_acpi_program_hp_params(struct pci_dev *dev); |
|
#else |
|
static inline int pci_acpi_program_hp_params(struct pci_dev *dev) |
|
{ |
|
return -ENODEV; |
|
} |
|
#endif |
|
|
|
#ifdef CONFIG_PCIEASPM |
|
extern const struct attribute_group aspm_ctrl_attr_group; |
|
#endif |
|
|
|
#endif /* DRIVERS_PCI_H */
|
|
|