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531 lines
14 KiB
531 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Cyclades PC300 synchronous serial card driver for Linux |
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* |
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* Copyright (C) 2000-2008 Krzysztof Halasa <[email protected]> |
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* |
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* For information see <https://www.kernel.org/pub/linux/utils/net/hdlc/>. |
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* |
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* Sources of information: |
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* Hitachi HD64572 SCA-II User's Manual |
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* Original Cyclades PC300 Linux driver |
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* |
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* This driver currently supports only PC300/RSV (V.24/V.35) and |
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* PC300/X21 cards. |
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*/ |
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/slab.h> |
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#include <linux/sched.h> |
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#include <linux/types.h> |
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#include <linux/fcntl.h> |
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#include <linux/in.h> |
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#include <linux/string.h> |
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#include <linux/errno.h> |
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#include <linux/init.h> |
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#include <linux/ioport.h> |
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#include <linux/moduleparam.h> |
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#include <linux/netdevice.h> |
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#include <linux/hdlc.h> |
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#include <linux/pci.h> |
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#include <linux/delay.h> |
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#include <asm/io.h> |
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#include "hd64572.h" |
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#undef DEBUG_PKT |
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#define DEBUG_RINGS |
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#define PC300_PLX_SIZE 0x80 /* PLX control window size (128 B) */ |
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#define PC300_SCA_SIZE 0x400 /* SCA window size (1 KB) */ |
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#define MAX_TX_BUFFERS 10 |
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static int pci_clock_freq = 33000000; |
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static int use_crystal_clock = 0; |
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static unsigned int CLOCK_BASE; |
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/* Masks to access the init_ctrl PLX register */ |
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#define PC300_CLKSEL_MASK (0x00000004UL) |
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#define PC300_CHMEDIA_MASK(port) (0x00000020UL << ((port) * 3)) |
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#define PC300_CTYPE_MASK (0x00000800UL) |
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enum { PC300_RSV = 1, PC300_X21, PC300_TE }; /* card types */ |
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/* |
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* PLX PCI9050-1 local configuration and shared runtime registers. |
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* This structure can be used to access 9050 registers (memory mapped). |
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*/ |
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typedef struct { |
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u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */ |
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u32 loc_rom_range; /* 10h : Local ROM Range */ |
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u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */ |
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u32 loc_rom_base; /* 24h : Local ROM Base */ |
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u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */ |
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u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */ |
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u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */ |
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u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */ |
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u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */ |
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}plx9050; |
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typedef struct port_s { |
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struct napi_struct napi; |
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struct net_device *netdev; |
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struct card_s *card; |
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spinlock_t lock; /* TX lock */ |
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sync_serial_settings settings; |
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int rxpart; /* partial frame received, next frame invalid*/ |
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unsigned short encoding; |
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unsigned short parity; |
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unsigned int iface; |
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u16 rxin; /* rx ring buffer 'in' pointer */ |
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u16 txin; /* tx ring buffer 'in' and 'last' pointers */ |
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u16 txlast; |
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u8 rxs, txs, tmc; /* SCA registers */ |
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u8 chan; /* physical port # - 0 or 1 */ |
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}port_t; |
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typedef struct card_s { |
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int type; /* RSV, X21, etc. */ |
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int n_ports; /* 1 or 2 ports */ |
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u8 __iomem *rambase; /* buffer memory base (virtual) */ |
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u8 __iomem *scabase; /* SCA memory base (virtual) */ |
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plx9050 __iomem *plxbase; /* PLX registers memory base (virtual) */ |
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u32 init_ctrl_value; /* Saved value - 9050 bug workaround */ |
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u16 rx_ring_buffers; /* number of buffers in a ring */ |
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u16 tx_ring_buffers; |
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u16 buff_offset; /* offset of first buffer of first channel */ |
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u8 irq; /* interrupt request level */ |
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port_t ports[2]; |
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}card_t; |
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#define get_port(card, port) ((port) < (card)->n_ports ? \ |
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(&(card)->ports[port]) : (NULL)) |
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#include "hd64572.c" |
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static void pc300_set_iface(port_t *port) |
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{ |
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card_t *card = port->card; |
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u32 __iomem * init_ctrl = &card->plxbase->init_ctrl; |
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u16 msci = get_msci(port); |
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u8 rxs = port->rxs & CLK_BRG_MASK; |
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u8 txs = port->txs & CLK_BRG_MASK; |
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sca_out(EXS_TES1, (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS, |
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port->card); |
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switch(port->settings.clock_type) { |
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case CLOCK_INT: |
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rxs |= CLK_BRG; /* BRG output */ |
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txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */ |
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break; |
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case CLOCK_TXINT: |
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rxs |= CLK_LINE; /* RXC input */ |
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txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */ |
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break; |
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case CLOCK_TXFROMRX: |
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rxs |= CLK_LINE; /* RXC input */ |
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txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */ |
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break; |
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default: /* EXTernal clock */ |
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rxs |= CLK_LINE; /* RXC input */ |
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txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */ |
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break; |
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} |
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port->rxs = rxs; |
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port->txs = txs; |
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sca_out(rxs, msci + RXS, card); |
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sca_out(txs, msci + TXS, card); |
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sca_set_port(port); |
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if (port->card->type == PC300_RSV) { |
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if (port->iface == IF_IFACE_V35) |
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writel(card->init_ctrl_value | |
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PC300_CHMEDIA_MASK(port->chan), init_ctrl); |
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else |
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writel(card->init_ctrl_value & |
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~PC300_CHMEDIA_MASK(port->chan), init_ctrl); |
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} |
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} |
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static int pc300_open(struct net_device *dev) |
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{ |
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port_t *port = dev_to_port(dev); |
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int result = hdlc_open(dev); |
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if (result) |
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return result; |
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sca_open(dev); |
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pc300_set_iface(port); |
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return 0; |
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} |
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static int pc300_close(struct net_device *dev) |
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{ |
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sca_close(dev); |
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hdlc_close(dev); |
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return 0; |
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} |
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static int pc300_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
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{ |
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const size_t size = sizeof(sync_serial_settings); |
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sync_serial_settings new_line; |
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sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; |
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int new_type; |
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port_t *port = dev_to_port(dev); |
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#ifdef DEBUG_RINGS |
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if (cmd == SIOCDEVPRIVATE) { |
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sca_dump_rings(dev); |
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return 0; |
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} |
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#endif |
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if (cmd != SIOCWANDEV) |
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return hdlc_ioctl(dev, ifr, cmd); |
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if (ifr->ifr_settings.type == IF_GET_IFACE) { |
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ifr->ifr_settings.type = port->iface; |
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if (ifr->ifr_settings.size < size) { |
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ifr->ifr_settings.size = size; /* data size wanted */ |
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return -ENOBUFS; |
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} |
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if (copy_to_user(line, &port->settings, size)) |
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return -EFAULT; |
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return 0; |
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} |
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if (port->card->type == PC300_X21 && |
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(ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL || |
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ifr->ifr_settings.type == IF_IFACE_X21)) |
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new_type = IF_IFACE_X21; |
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else if (port->card->type == PC300_RSV && |
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(ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL || |
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ifr->ifr_settings.type == IF_IFACE_V35)) |
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new_type = IF_IFACE_V35; |
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else if (port->card->type == PC300_RSV && |
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ifr->ifr_settings.type == IF_IFACE_V24) |
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new_type = IF_IFACE_V24; |
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else |
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return hdlc_ioctl(dev, ifr, cmd); |
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if (!capable(CAP_NET_ADMIN)) |
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return -EPERM; |
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if (copy_from_user(&new_line, line, size)) |
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return -EFAULT; |
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if (new_line.clock_type != CLOCK_EXT && |
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new_line.clock_type != CLOCK_TXFROMRX && |
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new_line.clock_type != CLOCK_INT && |
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new_line.clock_type != CLOCK_TXINT) |
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return -EINVAL; /* No such clock setting */ |
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if (new_line.loopback != 0 && new_line.loopback != 1) |
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return -EINVAL; |
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memcpy(&port->settings, &new_line, size); /* Update settings */ |
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port->iface = new_type; |
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pc300_set_iface(port); |
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return 0; |
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} |
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static void pc300_pci_remove_one(struct pci_dev *pdev) |
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{ |
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int i; |
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card_t *card = pci_get_drvdata(pdev); |
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for (i = 0; i < 2; i++) |
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if (card->ports[i].card) |
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unregister_hdlc_device(card->ports[i].netdev); |
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if (card->irq) |
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free_irq(card->irq, card); |
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if (card->rambase) |
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iounmap(card->rambase); |
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if (card->scabase) |
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iounmap(card->scabase); |
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if (card->plxbase) |
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iounmap(card->plxbase); |
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pci_release_regions(pdev); |
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pci_disable_device(pdev); |
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if (card->ports[0].netdev) |
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free_netdev(card->ports[0].netdev); |
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if (card->ports[1].netdev) |
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free_netdev(card->ports[1].netdev); |
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kfree(card); |
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} |
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static const struct net_device_ops pc300_ops = { |
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.ndo_open = pc300_open, |
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.ndo_stop = pc300_close, |
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.ndo_start_xmit = hdlc_start_xmit, |
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.ndo_do_ioctl = pc300_ioctl, |
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}; |
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static int pc300_pci_init_one(struct pci_dev *pdev, |
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const struct pci_device_id *ent) |
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{ |
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card_t *card; |
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u32 __iomem *p; |
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int i; |
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u32 ramsize; |
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u32 ramphys; /* buffer memory base */ |
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u32 scaphys; /* SCA memory base */ |
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u32 plxphys; /* PLX registers memory base */ |
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i = pci_enable_device(pdev); |
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if (i) |
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return i; |
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i = pci_request_regions(pdev, "PC300"); |
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if (i) { |
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pci_disable_device(pdev); |
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return i; |
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} |
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card = kzalloc(sizeof(card_t), GFP_KERNEL); |
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if (card == NULL) { |
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pci_release_regions(pdev); |
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pci_disable_device(pdev); |
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return -ENOBUFS; |
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} |
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pci_set_drvdata(pdev, card); |
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if (pci_resource_len(pdev, 0) != PC300_PLX_SIZE || |
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pci_resource_len(pdev, 2) != PC300_SCA_SIZE || |
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pci_resource_len(pdev, 3) < 16384) { |
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pr_err("invalid card EEPROM parameters\n"); |
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pc300_pci_remove_one(pdev); |
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return -EFAULT; |
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} |
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plxphys = pci_resource_start(pdev, 0) & PCI_BASE_ADDRESS_MEM_MASK; |
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card->plxbase = ioremap(plxphys, PC300_PLX_SIZE); |
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scaphys = pci_resource_start(pdev, 2) & PCI_BASE_ADDRESS_MEM_MASK; |
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card->scabase = ioremap(scaphys, PC300_SCA_SIZE); |
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ramphys = pci_resource_start(pdev, 3) & PCI_BASE_ADDRESS_MEM_MASK; |
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card->rambase = pci_ioremap_bar(pdev, 3); |
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if (card->plxbase == NULL || |
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card->scabase == NULL || |
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card->rambase == NULL) { |
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pr_err("ioremap() failed\n"); |
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pc300_pci_remove_one(pdev); |
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return -ENOMEM; |
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} |
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/* PLX PCI 9050 workaround for local configuration register read bug */ |
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pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, scaphys); |
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card->init_ctrl_value = readl(&((plx9050 __iomem *)card->scabase)->init_ctrl); |
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pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, plxphys); |
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if (pdev->device == PCI_DEVICE_ID_PC300_TE_1 || |
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pdev->device == PCI_DEVICE_ID_PC300_TE_2) |
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card->type = PC300_TE; /* not fully supported */ |
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else if (card->init_ctrl_value & PC300_CTYPE_MASK) |
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card->type = PC300_X21; |
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else |
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card->type = PC300_RSV; |
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if (pdev->device == PCI_DEVICE_ID_PC300_RX_1 || |
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pdev->device == PCI_DEVICE_ID_PC300_TE_1) |
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card->n_ports = 1; |
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else |
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card->n_ports = 2; |
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for (i = 0; i < card->n_ports; i++) |
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if (!(card->ports[i].netdev = alloc_hdlcdev(&card->ports[i]))) { |
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pr_err("unable to allocate memory\n"); |
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pc300_pci_remove_one(pdev); |
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return -ENOMEM; |
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} |
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/* Reset PLX */ |
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p = &card->plxbase->init_ctrl; |
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writel(card->init_ctrl_value | 0x40000000, p); |
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readl(p); /* Flush the write - do not use sca_flush */ |
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udelay(1); |
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writel(card->init_ctrl_value, p); |
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readl(p); /* Flush the write - do not use sca_flush */ |
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udelay(1); |
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/* Reload Config. Registers from EEPROM */ |
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writel(card->init_ctrl_value | 0x20000000, p); |
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readl(p); /* Flush the write - do not use sca_flush */ |
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udelay(1); |
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writel(card->init_ctrl_value, p); |
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readl(p); /* Flush the write - do not use sca_flush */ |
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udelay(1); |
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ramsize = sca_detect_ram(card, card->rambase, |
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pci_resource_len(pdev, 3)); |
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if (use_crystal_clock) |
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card->init_ctrl_value &= ~PC300_CLKSEL_MASK; |
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else |
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card->init_ctrl_value |= PC300_CLKSEL_MASK; |
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writel(card->init_ctrl_value, &card->plxbase->init_ctrl); |
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/* number of TX + RX buffers for one port */ |
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i = ramsize / (card->n_ports * (sizeof(pkt_desc) + HDLC_MAX_MRU)); |
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card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS); |
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card->rx_ring_buffers = i - card->tx_ring_buffers; |
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card->buff_offset = card->n_ports * sizeof(pkt_desc) * |
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(card->tx_ring_buffers + card->rx_ring_buffers); |
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pr_info("PC300/%s, %u KB RAM at 0x%x, IRQ%u, using %u TX + %u RX packets rings\n", |
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card->type == PC300_X21 ? "X21" : |
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card->type == PC300_TE ? "TE" : "RSV", |
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ramsize / 1024, ramphys, pdev->irq, |
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card->tx_ring_buffers, card->rx_ring_buffers); |
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if (card->tx_ring_buffers < 1) { |
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pr_err("RAM test failed\n"); |
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pc300_pci_remove_one(pdev); |
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return -EFAULT; |
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} |
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/* Enable interrupts on the PCI bridge, LINTi1 active low */ |
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writew(0x0041, &card->plxbase->intr_ctrl_stat); |
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/* Allocate IRQ */ |
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if (request_irq(pdev->irq, sca_intr, IRQF_SHARED, "pc300", card)) { |
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pr_warn("could not allocate IRQ%d\n", pdev->irq); |
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pc300_pci_remove_one(pdev); |
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return -EBUSY; |
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} |
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card->irq = pdev->irq; |
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sca_init(card, 0); |
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// COTE not set - allows better TX DMA settings |
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// sca_out(sca_in(PCR, card) | PCR_COTE, PCR, card); |
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sca_out(0x10, BTCR, card); |
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for (i = 0; i < card->n_ports; i++) { |
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port_t *port = &card->ports[i]; |
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struct net_device *dev = port->netdev; |
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hdlc_device *hdlc = dev_to_hdlc(dev); |
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port->chan = i; |
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spin_lock_init(&port->lock); |
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dev->irq = card->irq; |
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dev->mem_start = ramphys; |
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dev->mem_end = ramphys + ramsize - 1; |
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dev->tx_queue_len = 50; |
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dev->netdev_ops = &pc300_ops; |
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hdlc->attach = sca_attach; |
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hdlc->xmit = sca_xmit; |
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port->settings.clock_type = CLOCK_EXT; |
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port->card = card; |
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if (card->type == PC300_X21) |
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port->iface = IF_IFACE_X21; |
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else |
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port->iface = IF_IFACE_V35; |
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sca_init_port(port); |
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if (register_hdlc_device(dev)) { |
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pr_err("unable to register hdlc device\n"); |
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port->card = NULL; |
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pc300_pci_remove_one(pdev); |
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return -ENOBUFS; |
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} |
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netdev_info(dev, "PC300 channel %d\n", port->chan); |
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} |
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return 0; |
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} |
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static const struct pci_device_id pc300_pci_tbl[] = { |
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{ PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_1, PCI_ANY_ID, |
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PCI_ANY_ID, 0, 0, 0 }, |
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{ PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_2, PCI_ANY_ID, |
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PCI_ANY_ID, 0, 0, 0 }, |
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{ PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_1, PCI_ANY_ID, |
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PCI_ANY_ID, 0, 0, 0 }, |
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{ PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_2, PCI_ANY_ID, |
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PCI_ANY_ID, 0, 0, 0 }, |
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{ 0, } |
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}; |
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static struct pci_driver pc300_pci_driver = { |
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.name = "PC300", |
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.id_table = pc300_pci_tbl, |
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.probe = pc300_pci_init_one, |
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.remove = pc300_pci_remove_one, |
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}; |
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static int __init pc300_init_module(void) |
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{ |
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if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) { |
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pr_err("Invalid PCI clock frequency\n"); |
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return -EINVAL; |
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} |
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if (use_crystal_clock != 0 && use_crystal_clock != 1) { |
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pr_err("Invalid 'use_crystal_clock' value\n"); |
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return -EINVAL; |
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} |
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CLOCK_BASE = use_crystal_clock ? 24576000 : pci_clock_freq; |
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return pci_register_driver(&pc300_pci_driver); |
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} |
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static void __exit pc300_cleanup_module(void) |
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{ |
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pci_unregister_driver(&pc300_pci_driver); |
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} |
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MODULE_AUTHOR("Krzysztof Halasa <[email protected]>"); |
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MODULE_DESCRIPTION("Cyclades PC300 serial port driver"); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_DEVICE_TABLE(pci, pc300_pci_tbl); |
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module_param(pci_clock_freq, int, 0444); |
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MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz"); |
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module_param(use_crystal_clock, int, 0444); |
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MODULE_PARM_DESC(use_crystal_clock, |
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"Use 24.576 MHz clock instead of PCI clock"); |
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module_init(pc300_init_module); |
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module_exit(pc300_cleanup_module);
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