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67 lines
1.8 KiB
67 lines
1.8 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (c) 2013, Steffen Trumtrar <[email protected]> |
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* |
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* based on drivers/clk/tegra/clk.h |
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*/ |
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#ifndef __SOCFPGA_CLK_H |
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#define __SOCFPGA_CLK_H |
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#include <linux/clk-provider.h> |
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/* Clock Manager offsets */ |
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#define CLKMGR_CTRL 0x0 |
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#define CLKMGR_BYPASS 0x4 |
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#define CLKMGR_DBCTRL 0x10 |
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#define CLKMGR_L4SRC 0x70 |
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#define CLKMGR_PERPLL_SRC 0xAC |
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#define SOCFPGA_MAX_PARENTS 5 |
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#define streq(a, b) (strcmp((a), (b)) == 0) |
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#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ |
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((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) |
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#define SYSMGR_SDMMC_CTRL_SET_AS10(smplsel, drvsel) \ |
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((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0)) |
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extern void __iomem *clk_mgr_base_addr; |
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extern void __iomem *clk_mgr_a10_base_addr; |
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void __init socfpga_pll_init(struct device_node *node); |
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void __init socfpga_periph_init(struct device_node *node); |
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void __init socfpga_gate_init(struct device_node *node); |
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void socfpga_a10_pll_init(struct device_node *node); |
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void socfpga_a10_periph_init(struct device_node *node); |
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void socfpga_a10_gate_init(struct device_node *node); |
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struct socfpga_pll { |
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struct clk_gate hw; |
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}; |
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struct socfpga_gate_clk { |
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struct clk_gate hw; |
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char *parent_name; |
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u32 fixed_div; |
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void __iomem *div_reg; |
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void __iomem *bypass_reg; |
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struct regmap *sys_mgr_base_addr; |
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u32 width; /* only valid if div_reg != 0 */ |
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u32 shift; /* only valid if div_reg != 0 */ |
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u32 bypass_shift; /* only valid if bypass_reg != 0 */ |
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u32 clk_phase[2]; |
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}; |
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struct socfpga_periph_clk { |
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struct clk_gate hw; |
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char *parent_name; |
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u32 fixed_div; |
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void __iomem *div_reg; |
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void __iomem *bypass_reg; |
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u32 width; /* only valid if div_reg != 0 */ |
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u32 shift; /* only valid if div_reg != 0 */ |
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u32 bypass_shift; /* only valid if bypass_reg != 0 */ |
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}; |
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#endif /* SOCFPGA_CLK_H */
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