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282 lines
7.3 KiB
282 lines
7.3 KiB
/* SPDX-License-Identifier: GPL-2.0+ */ |
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/* |
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* Copyright 2011 Freescale Semiconductor, Inc. |
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* Andy Fleming <[email protected]> |
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* |
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* This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h |
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*/ |
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#ifndef _PHY_H |
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#define _PHY_H |
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#include <dm.h> |
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#include <linux/list.h> |
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#include <linux/mii.h> |
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#include <linux/ethtool.h> |
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#include <linux/mdio.h> |
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#include <phy_interface.h> |
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#define PHY_FIXED_ID 0xa5a55a5a |
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#define PHY_MAX_ADDR 32 |
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#define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */ |
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#define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \ |
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SUPPORTED_TP | \ |
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SUPPORTED_MII) |
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#define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \ |
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SUPPORTED_10baseT_Full) |
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#define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \ |
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SUPPORTED_100baseT_Full) |
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#define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \ |
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SUPPORTED_1000baseT_Full) |
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#define PHY_BASIC_FEATURES (PHY_10BT_FEATURES | \ |
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PHY_100BT_FEATURES | \ |
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PHY_DEFAULT_FEATURES) |
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#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \ |
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PHY_1000BT_FEATURES) |
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#define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \ |
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SUPPORTED_10000baseT_Full) |
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#ifndef PHY_ANEG_TIMEOUT |
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#define PHY_ANEG_TIMEOUT 4000 |
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#endif |
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struct phy_device; |
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#define MDIO_NAME_LEN 32 |
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struct mii_dev { |
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struct list_head link; |
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char name[MDIO_NAME_LEN]; |
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void *priv; |
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int (*read)(struct mii_dev *bus, int addr, int devad, int reg); |
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int (*write)(struct mii_dev *bus, int addr, int devad, int reg, |
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u16 val); |
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int (*reset)(struct mii_dev *bus); |
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struct phy_device *phymap[PHY_MAX_ADDR]; |
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u32 phy_mask; |
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}; |
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/* struct phy_driver: a structure which defines PHY behavior |
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* |
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* uid will contain a number which represents the PHY. During |
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* startup, the driver will poll the PHY to find out what its |
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* UID--as defined by registers 2 and 3--is. The 32-bit result |
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* gotten from the PHY will be masked to |
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* discard any bits which may change based on revision numbers |
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* unimportant to functionality |
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* |
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*/ |
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struct phy_driver { |
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char *name; |
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unsigned int uid; |
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unsigned int mask; |
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unsigned int mmds; |
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u32 features; |
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/* Called to do any driver startup necessities */ |
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/* Will be called during phy_connect */ |
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int (*probe)(struct phy_device *phydev); |
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/* Called to configure the PHY, and modify the controller |
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* based on the results. Should be called after phy_connect */ |
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int (*config)(struct phy_device *phydev); |
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/* Called when starting up the controller */ |
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int (*startup)(struct phy_device *phydev); |
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/* Called when bringing down the controller */ |
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int (*shutdown)(struct phy_device *phydev); |
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int (*readext)(struct phy_device *phydev, int addr, int devad, int reg); |
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int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg, |
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u16 val); |
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struct list_head list; |
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}; |
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struct phy_device { |
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/* Information about the PHY type */ |
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/* And management functions */ |
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struct mii_dev *bus; |
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struct phy_driver *drv; |
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void *priv; |
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#ifdef CONFIG_DM_ETH |
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struct udevice *dev; |
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ofnode node; |
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#else |
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struct eth_device *dev; |
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#endif |
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/* forced speed & duplex (no autoneg) |
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* partner speed & duplex & pause (autoneg) |
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*/ |
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int speed; |
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int duplex; |
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/* The most recently read link state */ |
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int link; |
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int port; |
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phy_interface_t interface; |
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u32 advertising; |
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u32 supported; |
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u32 mmds; |
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int autoneg; |
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int addr; |
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int pause; |
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int asym_pause; |
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u32 phy_id; |
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u32 flags; |
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}; |
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struct fixed_link { |
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int phy_id; |
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int duplex; |
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int link_speed; |
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int pause; |
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int asym_pause; |
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}; |
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static inline int phy_read(struct phy_device *phydev, int devad, int regnum) |
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{ |
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struct mii_dev *bus = phydev->bus; |
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return bus->read(bus, phydev->addr, devad, regnum); |
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} |
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static inline int phy_write(struct phy_device *phydev, int devad, int regnum, |
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u16 val) |
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{ |
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struct mii_dev *bus = phydev->bus; |
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return bus->write(bus, phydev->addr, devad, regnum, val); |
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} |
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#ifdef CONFIG_PHYLIB_10G |
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extern struct phy_driver gen10g_driver; |
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/* For now, XGMII is the only 10G interface */ |
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static inline int is_10g_interface(phy_interface_t interface) |
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{ |
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return interface == PHY_INTERFACE_MODE_XGMII; |
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} |
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#endif |
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int phy_init(void); |
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int phy_reset(struct phy_device *phydev); |
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struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask, |
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phy_interface_t interface); |
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#ifdef CONFIG_DM_ETH |
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void phy_connect_dev(struct phy_device *phydev, struct udevice *dev); |
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struct phy_device *phy_connect(struct mii_dev *bus, int addr, |
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struct udevice *dev, |
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phy_interface_t interface); |
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static inline ofnode phy_get_ofnode(struct phy_device *phydev) |
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{ |
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if (ofnode_valid(phydev->node)) |
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return phydev->node; |
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else |
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return dev_ofnode(phydev->dev); |
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} |
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#else |
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void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev); |
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struct phy_device *phy_connect(struct mii_dev *bus, int addr, |
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struct eth_device *dev, |
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phy_interface_t interface); |
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static inline ofnode phy_get_ofnode(struct phy_device *phydev) |
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{ |
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return ofnode_null(); |
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} |
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#endif |
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int phy_startup(struct phy_device *phydev); |
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int phy_config(struct phy_device *phydev); |
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int phy_shutdown(struct phy_device *phydev); |
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int phy_register(struct phy_driver *drv); |
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int phy_set_supported(struct phy_device *phydev, u32 max_speed); |
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int genphy_config_aneg(struct phy_device *phydev); |
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int genphy_restart_aneg(struct phy_device *phydev); |
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int genphy_update_link(struct phy_device *phydev); |
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int genphy_parse_link(struct phy_device *phydev); |
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int genphy_config(struct phy_device *phydev); |
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int genphy_startup(struct phy_device *phydev); |
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int genphy_shutdown(struct phy_device *phydev); |
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int gen10g_config(struct phy_device *phydev); |
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int gen10g_startup(struct phy_device *phydev); |
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int gen10g_shutdown(struct phy_device *phydev); |
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int gen10g_discover_mmds(struct phy_device *phydev); |
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int phy_b53_init(void); |
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int phy_mv88e61xx_init(void); |
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int phy_aquantia_init(void); |
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int phy_atheros_init(void); |
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int phy_broadcom_init(void); |
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int phy_cortina_init(void); |
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int phy_davicom_init(void); |
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int phy_et1011c_init(void); |
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int phy_lxt_init(void); |
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int phy_marvell_init(void); |
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int phy_micrel_ksz8xxx_init(void); |
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int phy_micrel_ksz90x1_init(void); |
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int phy_meson_gxl_init(void); |
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int phy_natsemi_init(void); |
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int phy_realtek_init(void); |
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int phy_smsc_init(void); |
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int phy_teranetics_init(void); |
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int phy_ti_init(void); |
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int phy_vitesse_init(void); |
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int phy_xilinx_init(void); |
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int phy_mscc_init(void); |
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int phy_fixed_init(void); |
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int board_phy_config(struct phy_device *phydev); |
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int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id); |
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/** |
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* phy_get_interface_by_name() - Look up a PHY interface name |
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* |
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* @str: PHY interface name, e.g. "mii" |
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* @return PHY_INTERFACE_MODE_... value, or -1 if not found |
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*/ |
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int phy_get_interface_by_name(const char *str); |
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/** |
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* phy_interface_is_rgmii - Convenience function for testing if a PHY interface |
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* is RGMII (all variants) |
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* @phydev: the phy_device struct |
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*/ |
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static inline bool phy_interface_is_rgmii(struct phy_device *phydev) |
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{ |
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return phydev->interface >= PHY_INTERFACE_MODE_RGMII && |
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phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; |
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} |
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/** |
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* phy_interface_is_sgmii - Convenience function for testing if a PHY interface |
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* is SGMII (all variants) |
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* @phydev: the phy_device struct |
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*/ |
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static inline bool phy_interface_is_sgmii(struct phy_device *phydev) |
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{ |
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return phydev->interface >= PHY_INTERFACE_MODE_SGMII && |
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phydev->interface <= PHY_INTERFACE_MODE_QSGMII; |
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} |
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/* PHY UIDs for various PHYs that are referenced in external code */ |
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#define PHY_UID_CS4340 0x13e51002 |
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#define PHY_UID_CS4223 0x03e57003 |
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#define PHY_UID_TN2020 0x00a19410 |
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#endif
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