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278 lines
7.7 KiB
278 lines
7.7 KiB
/* SPDX-License-Identifier: GPL-2.0+ */ |
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/* |
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* Marvell MMC/SD/SDIO driver |
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* |
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* (C) Copyright 2012 |
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* Marvell Semiconductor <www.marvell.com> |
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* Written-by: Maen Suleiman, Gerald Kerma |
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*/ |
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#ifndef __MVEBU_MMC_H__ |
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#define __MVEBU_MMC_H__ |
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/* needed for the mmc_cfg definition */ |
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#include <mmc.h> |
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#define MMC_BLOCK_SIZE 512 |
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/* |
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* Clock rates |
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*/ |
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#define MVEBU_MMC_CLOCKRATE_MAX 50000000 |
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#define MVEBU_MMC_BASE_DIV_MAX 0x7ff |
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#define MVEBU_MMC_BASE_FAST_CLOCK CONFIG_SYS_TCLK |
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#define MVEBU_MMC_BASE_FAST_CLK_100 100000000 |
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#define MVEBU_MMC_BASE_FAST_CLK_200 200000000 |
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/* SDIO register */ |
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#define SDIO_SYS_ADDR_LOW 0x000 |
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#define SDIO_SYS_ADDR_HI 0x004 |
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#define SDIO_BLK_SIZE 0x008 |
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#define SDIO_BLK_COUNT 0x00c |
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#define SDIO_ARG_LOW 0x010 |
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#define SDIO_ARG_HI 0x014 |
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#define SDIO_XFER_MODE 0x018 |
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#define SDIO_CMD 0x01c |
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#define SDIO_RSP(i) (0x020 + ((i)<<2)) |
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#define SDIO_RSP0 0x020 |
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#define SDIO_RSP1 0x024 |
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#define SDIO_RSP2 0x028 |
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#define SDIO_RSP3 0x02c |
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#define SDIO_RSP4 0x030 |
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#define SDIO_RSP5 0x034 |
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#define SDIO_RSP6 0x038 |
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#define SDIO_RSP7 0x03c |
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#define SDIO_BUF_DATA_PORT 0x040 |
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#define SDIO_RSVED 0x044 |
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#define SDIO_HW_STATE 0x048 |
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#define SDIO_PRESENT_STATE0 0x048 |
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#define SDIO_PRESENT_STATE1 0x04c |
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#define SDIO_HOST_CTRL 0x050 |
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#define SDIO_BLK_GAP_CTRL 0x054 |
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#define SDIO_CLK_CTRL 0x058 |
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#define SDIO_SW_RESET 0x05c |
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#define SDIO_NOR_INTR_STATUS 0x060 |
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#define SDIO_ERR_INTR_STATUS 0x064 |
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#define SDIO_NOR_STATUS_EN 0x068 |
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#define SDIO_ERR_STATUS_EN 0x06c |
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#define SDIO_NOR_INTR_EN 0x070 |
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#define SDIO_ERR_INTR_EN 0x074 |
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#define SDIO_AUTOCMD12_ERR_STATUS 0x078 |
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#define SDIO_CURR_BYTE_LEFT 0x07c |
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#define SDIO_CURR_BLK_LEFT 0x080 |
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#define SDIO_AUTOCMD12_ARG_LOW 0x084 |
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#define SDIO_AUTOCMD12_ARG_HI 0x088 |
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#define SDIO_AUTOCMD12_INDEX 0x08c |
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#define SDIO_AUTO_RSP(i) (0x090 + ((i)<<2)) |
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#define SDIO_AUTO_RSP0 0x090 |
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#define SDIO_AUTO_RSP1 0x094 |
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#define SDIO_AUTO_RSP2 0x098 |
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#define SDIO_CLK_DIV 0x128 |
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#define WINDOW_CTRL(i) (0x108 + ((i) << 3)) |
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#define WINDOW_BASE(i) (0x10c + ((i) << 3)) |
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/* SDIO_PRESENT_STATE */ |
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#define CARD_BUSY (1 << 1) |
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#define CMD_INHIBIT (1 << 0) |
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#define CMD_TXACTIVE (1 << 8) |
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#define CMD_RXACTIVE (1 << 9) |
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#define CMD_FIFO_EMPTY (1 << 13) |
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#define CMD_AUTOCMD12ACTIVE (1 << 14) |
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#define CMD_BUS_BUSY (CMD_AUTOCMD12ACTIVE | \ |
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CMD_RXACTIVE | \ |
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CMD_TXACTIVE | \ |
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CMD_INHIBIT | \ |
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CARD_BUSY) |
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/* |
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* SDIO_CMD |
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*/ |
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#define SDIO_CMD_RSP_NONE (0 << 0) |
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#define SDIO_CMD_RSP_136 (1 << 0) |
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#define SDIO_CMD_RSP_48 (2 << 0) |
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#define SDIO_CMD_RSP_48BUSY (3 << 0) |
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#define SDIO_CMD_CHECK_DATACRC16 (1 << 2) |
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#define SDIO_CMD_CHECK_CMDCRC (1 << 3) |
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#define SDIO_CMD_INDX_CHECK (1 << 4) |
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#define SDIO_CMD_DATA_PRESENT (1 << 5) |
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#define SDIO_UNEXPECTED_RESP (1 << 7) |
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#define SDIO_CMD_INDEX(x) ((x) << 8) |
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/* |
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* SDIO_XFER_MODE |
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*/ |
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#define SDIO_XFER_MODE_STOP_CLK (1 << 5) |
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#define SDIO_XFER_MODE_HW_WR_DATA_EN (1 << 1) |
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#define SDIO_XFER_MODE_AUTO_CMD12 (1 << 2) |
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#define SDIO_XFER_MODE_INT_CHK_EN (1 << 3) |
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#define SDIO_XFER_MODE_TO_HOST (1 << 4) |
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#define SDIO_XFER_MODE_DMA (0 << 6) |
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/* |
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* SDIO_HOST_CTRL |
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*/ |
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#define SDIO_HOST_CTRL_PUSH_PULL_EN (1 << 0) |
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#define SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY (0 << 1) |
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#define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY (1 << 1) |
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#define SDIO_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO (2 << 1) |
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#define SDIO_HOST_CTRL_CARD_TYPE_IO_MMC (3 << 1) |
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#define SDIO_HOST_CTRL_CARD_TYPE_MASK (3 << 1) |
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#define SDIO_HOST_CTRL_BIG_ENDIAN (1 << 3) |
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#define SDIO_HOST_CTRL_LSB_FIRST (1 << 4) |
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#define SDIO_HOST_CTRL_DATA_WIDTH_1_BIT (0 << 9) |
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#define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS (1 << 9) |
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#define SDIO_HOST_CTRL_HI_SPEED_EN (1 << 10) |
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#define SDIO_HOST_CTRL_TMOUT_MAX 0xf |
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#define SDIO_HOST_CTRL_TMOUT_MASK (0xf << 11) |
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#define SDIO_HOST_CTRL_TMOUT(x) ((x) << 11) |
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#define SDIO_HOST_CTRL_TMOUT_EN (1 << 15) |
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/* |
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* SDIO_SW_RESET |
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*/ |
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#define SDIO_SW_RESET_NOW (1 << 8) |
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/* |
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* Normal interrupt status bits |
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*/ |
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#define SDIO_NOR_ERROR (1 << 15) |
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#define SDIO_NOR_UNEXP_RSP (1 << 14) |
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#define SDIO_NOR_AUTOCMD12_DONE (1 << 13) |
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#define SDIO_NOR_SUSPEND_ON (1 << 12) |
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#define SDIO_NOR_LMB_FF_8W_AVAIL (1 << 11) |
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#define SDIO_NOR_LMB_FF_8W_FILLED (1 << 10) |
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#define SDIO_NOR_READ_WAIT_ON (1 << 9) |
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#define SDIO_NOR_CARD_INT (1 << 8) |
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#define SDIO_NOR_READ_READY (1 << 5) |
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#define SDIO_NOR_WRITE_READY (1 << 4) |
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#define SDIO_NOR_DMA_INI (1 << 3) |
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#define SDIO_NOR_BLK_GAP_EVT (1 << 2) |
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#define SDIO_NOR_XFER_DONE (1 << 1) |
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#define SDIO_NOR_CMD_DONE (1 << 0) |
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/* |
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* Error status bits |
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*/ |
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#define SDIO_ERR_CRC_STATUS (1 << 14) |
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#define SDIO_ERR_CRC_STARTBIT (1 << 13) |
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#define SDIO_ERR_CRC_ENDBIT (1 << 12) |
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#define SDIO_ERR_RESP_TBIT (1 << 11) |
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#define SDIO_ERR_XFER_SIZE (1 << 10) |
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#define SDIO_ERR_CMD_STARTBIT (1 << 9) |
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#define SDIO_ERR_AUTOCMD12 (1 << 8) |
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#define SDIO_ERR_DATA_ENDBIT (1 << 6) |
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#define SDIO_ERR_DATA_CRC (1 << 5) |
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#define SDIO_ERR_DATA_TIMEOUT (1 << 4) |
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#define SDIO_ERR_CMD_INDEX (1 << 3) |
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#define SDIO_ERR_CMD_ENDBIT (1 << 2) |
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#define SDIO_ERR_CMD_CRC (1 << 1) |
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#define SDIO_ERR_CMD_TIMEOUT (1 << 0) |
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/* enable all for polling */ |
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#define SDIO_POLL_MASK 0xffff |
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/* |
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* CMD12 error status bits |
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*/ |
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#define SDIO_AUTOCMD12_ERR_NOTEXE (1 << 0) |
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#define SDIO_AUTOCMD12_ERR_TIMEOUT (1 << 1) |
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#define SDIO_AUTOCMD12_ERR_CRC (1 << 2) |
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#define SDIO_AUTOCMD12_ERR_ENDBIT (1 << 3) |
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#define SDIO_AUTOCMD12_ERR_INDEX (1 << 4) |
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#define SDIO_AUTOCMD12_ERR_RESP_T_BIT (1 << 5) |
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#define SDIO_AUTOCMD12_ERR_RESP_STARTBIT (1 << 6) |
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#define MMC_RSP_PRESENT (1 << 0) |
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/* 136 bit response */ |
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#define MMC_RSP_136 (1 << 1) |
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/* expect valid crc */ |
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#define MMC_RSP_CRC (1 << 2) |
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/* card may send busy */ |
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#define MMC_RSP_BUSY (1 << 3) |
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/* response contains opcode */ |
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#define MMC_RSP_OPCODE (1 << 4) |
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#define MMC_BUSMODE_OPENDRAIN 1 |
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#define MMC_BUSMODE_PUSHPULL 2 |
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#define MMC_BUS_WIDTH_1 0 |
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#define MMC_BUS_WIDTH_4 2 |
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#define MMC_BUS_WIDTH_8 3 |
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/* Can the host do 4 bit transfers */ |
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#define MMC_CAP_4_BIT_DATA (1 << 0) |
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/* Can do MMC high-speed timing */ |
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#define MMC_CAP_MMC_HIGHSPEED (1 << 1) |
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/* Can do SD high-speed timing */ |
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#define MMC_CAP_SD_HIGHSPEED (1 << 2) |
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/* Can signal pending SDIO IRQs */ |
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#define MMC_CAP_SDIO_IRQ (1 << 3) |
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/* Talks only SPI protocols */ |
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#define MMC_CAP_SPI (1 << 4) |
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/* Needs polling for card-detection */ |
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#define MMC_CAP_NEEDS_POLL (1 << 5) |
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/* Can the host do 8 bit transfers */ |
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#define MMC_CAP_8_BIT_DATA (1 << 6) |
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/* Nonremovable e.g. eMMC */ |
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#define MMC_CAP_NONREMOVABLE (1 << 8) |
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/* Waits while card is busy */ |
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#define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) |
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/* Allow erase/trim commands */ |
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#define MMC_CAP_ERASE (1 << 10) |
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/* can support DDR mode at 1.8V */ |
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#define MMC_CAP_1_8V_DDR (1 << 11) |
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/* can support DDR mode at 1.2V */ |
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#define MMC_CAP_1_2V_DDR (1 << 12) |
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/* Can power off after boot */ |
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#define MMC_CAP_POWER_OFF_CARD (1 << 13) |
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/* CMD14/CMD19 bus width ok */ |
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#define MMC_CAP_BUS_WIDTH_TEST (1 << 14) |
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/* Host supports UHS SDR12 mode */ |
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#define MMC_CAP_UHS_SDR12 (1 << 15) |
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/* Host supports UHS SDR25 mode */ |
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#define MMC_CAP_UHS_SDR25 (1 << 16) |
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/* Host supports UHS SDR50 mode */ |
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#define MMC_CAP_UHS_SDR50 (1 << 17) |
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/* Host supports UHS SDR104 mode */ |
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#define MMC_CAP_UHS_SDR104 (1 << 18) |
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/* Host supports UHS DDR50 mode */ |
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#define MMC_CAP_UHS_DDR50 (1 << 19) |
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/* Host supports Driver Type A */ |
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#define MMC_CAP_DRIVER_TYPE_A (1 << 23) |
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/* Host supports Driver Type C */ |
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#define MMC_CAP_DRIVER_TYPE_C (1 << 24) |
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/* Host supports Driver Type D */ |
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#define MMC_CAP_DRIVER_TYPE_D (1 << 25) |
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/* CMD23 supported. */ |
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#define MMC_CAP_CMD23 (1 << 30) |
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/* Hardware reset */ |
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#define MMC_CAP_HW_RESET (1 << 31) |
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struct mvebu_mmc_cfg { |
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u32 mvebu_mmc_base; |
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u32 mvebu_mmc_clk; |
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u8 max_bus_width; |
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struct mmc_config cfg; |
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}; |
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/* |
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* Functions prototypes |
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*/ |
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int mvebu_mmc_init(bd_t *bis); |
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#endif /* __MVEBU_MMC_H__ */
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