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995 lines
24 KiB
995 lines
24 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Resource Director Technology(RDT) |
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* - Cache Allocation code. |
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* |
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* Copyright (C) 2016 Intel Corporation |
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* |
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* Authors: |
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* Fenghua Yu <[email protected]> |
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* Tony Luck <[email protected]> |
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* Vikas Shivappa <[email protected]> |
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* |
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* More information about RDT be found in the Intel (R) x86 Architecture |
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* Software Developer Manual June 2016, volume 3, section 17.17. |
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*/ |
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|
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#define pr_fmt(fmt) "resctrl: " fmt |
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|
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#include <linux/slab.h> |
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#include <linux/err.h> |
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#include <linux/cacheinfo.h> |
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#include <linux/cpuhotplug.h> |
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#include <asm/intel-family.h> |
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#include <asm/resctrl.h> |
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#include "internal.h" |
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/* Mutex to protect rdtgroup access. */ |
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DEFINE_MUTEX(rdtgroup_mutex); |
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|
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/* |
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* The cached resctrl_pqr_state is strictly per CPU and can never be |
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* updated from a remote CPU. Functions which modify the state |
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* are called with interrupts disabled and no preemption, which |
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* is sufficient for the protection. |
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*/ |
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DEFINE_PER_CPU(struct resctrl_pqr_state, pqr_state); |
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|
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/* |
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* Used to store the max resource name width and max resource data width |
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* to display the schemata in a tabular format |
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*/ |
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int max_name_width, max_data_width; |
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|
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/* |
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* Global boolean for rdt_alloc which is true if any |
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* resource allocation is enabled. |
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*/ |
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bool rdt_alloc_capable; |
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static void |
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mba_wrmsr_intel(struct rdt_domain *d, struct msr_param *m, |
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struct rdt_resource *r); |
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static void |
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cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r); |
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static void |
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mba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m, |
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struct rdt_resource *r); |
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#define domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.domains) |
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struct rdt_hw_resource rdt_resources_all[] = { |
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[RDT_RESOURCE_L3] = |
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{ |
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.r_resctrl = { |
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.rid = RDT_RESOURCE_L3, |
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.name = "L3", |
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.cache_level = 3, |
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.cache = { |
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.min_cbm_bits = 1, |
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}, |
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.domains = domain_init(RDT_RESOURCE_L3), |
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.parse_ctrlval = parse_cbm, |
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.format_str = "%d=%0*x", |
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.fflags = RFTYPE_RES_CACHE, |
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}, |
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.msr_base = MSR_IA32_L3_CBM_BASE, |
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.msr_update = cat_wrmsr, |
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}, |
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[RDT_RESOURCE_L2] = |
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{ |
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.r_resctrl = { |
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.rid = RDT_RESOURCE_L2, |
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.name = "L2", |
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.cache_level = 2, |
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.cache = { |
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.min_cbm_bits = 1, |
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}, |
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.domains = domain_init(RDT_RESOURCE_L2), |
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.parse_ctrlval = parse_cbm, |
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.format_str = "%d=%0*x", |
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.fflags = RFTYPE_RES_CACHE, |
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}, |
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.msr_base = MSR_IA32_L2_CBM_BASE, |
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.msr_update = cat_wrmsr, |
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}, |
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[RDT_RESOURCE_MBA] = |
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{ |
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.r_resctrl = { |
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.rid = RDT_RESOURCE_MBA, |
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.name = "MB", |
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.cache_level = 3, |
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.domains = domain_init(RDT_RESOURCE_MBA), |
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.parse_ctrlval = parse_bw, |
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.format_str = "%d=%*u", |
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.fflags = RFTYPE_RES_MB, |
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}, |
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}, |
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}; |
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/* |
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* cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs |
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* as they do not have CPUID enumeration support for Cache allocation. |
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* The check for Vendor/Family/Model is not enough to guarantee that |
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* the MSRs won't #GP fault because only the following SKUs support |
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* CAT: |
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* Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz |
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* Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz |
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* Intel(R) Xeon(R) CPU E5-2628L v3 @ 2.00GHz |
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* Intel(R) Xeon(R) CPU E5-2618L v3 @ 2.30GHz |
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* Intel(R) Xeon(R) CPU E5-2608L v3 @ 2.00GHz |
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* Intel(R) Xeon(R) CPU E5-2658A v3 @ 2.20GHz |
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* |
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* Probe by trying to write the first of the L3 cache mask registers |
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* and checking that the bits stick. Max CLOSids is always 4 and max cbm length |
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* is always 20 on hsw server parts. The minimum cache bitmask length |
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* allowed for HSW server is always 2 bits. Hardcode all of them. |
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*/ |
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static inline void cache_alloc_hsw_probe(void) |
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{ |
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struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_L3]; |
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struct rdt_resource *r = &hw_res->r_resctrl; |
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u32 l, h, max_cbm = BIT_MASK(20) - 1; |
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if (wrmsr_safe(MSR_IA32_L3_CBM_BASE, max_cbm, 0)) |
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return; |
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rdmsr(MSR_IA32_L3_CBM_BASE, l, h); |
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/* If all the bits were set in MSR, return success */ |
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if (l != max_cbm) |
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return; |
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hw_res->num_closid = 4; |
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r->default_ctrl = max_cbm; |
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r->cache.cbm_len = 20; |
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r->cache.shareable_bits = 0xc0000; |
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r->cache.min_cbm_bits = 2; |
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r->alloc_capable = true; |
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r->alloc_enabled = true; |
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rdt_alloc_capable = true; |
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} |
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bool is_mba_sc(struct rdt_resource *r) |
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{ |
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if (!r) |
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return rdt_resources_all[RDT_RESOURCE_MBA].r_resctrl.membw.mba_sc; |
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return r->membw.mba_sc; |
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} |
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/* |
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* rdt_get_mb_table() - get a mapping of bandwidth(b/w) percentage values |
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* exposed to user interface and the h/w understandable delay values. |
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* |
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* The non-linear delay values have the granularity of power of two |
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* and also the h/w does not guarantee a curve for configured delay |
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* values vs. actual b/w enforced. |
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* Hence we need a mapping that is pre calibrated so the user can |
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* express the memory b/w as a percentage value. |
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*/ |
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static inline bool rdt_get_mb_table(struct rdt_resource *r) |
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{ |
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/* |
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* There are no Intel SKUs as of now to support non-linear delay. |
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*/ |
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pr_info("MBA b/w map not implemented for cpu:%d, model:%d", |
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boot_cpu_data.x86, boot_cpu_data.x86_model); |
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return false; |
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} |
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static bool __get_mem_config_intel(struct rdt_resource *r) |
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{ |
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struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); |
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union cpuid_0x10_3_eax eax; |
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union cpuid_0x10_x_edx edx; |
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u32 ebx, ecx, max_delay; |
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cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full); |
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hw_res->num_closid = edx.split.cos_max + 1; |
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max_delay = eax.split.max_delay + 1; |
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r->default_ctrl = MAX_MBA_BW; |
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r->membw.arch_needs_linear = true; |
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if (ecx & MBA_IS_LINEAR) { |
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r->membw.delay_linear = true; |
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r->membw.min_bw = MAX_MBA_BW - max_delay; |
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r->membw.bw_gran = MAX_MBA_BW - max_delay; |
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} else { |
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if (!rdt_get_mb_table(r)) |
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return false; |
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r->membw.arch_needs_linear = false; |
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} |
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r->data_width = 3; |
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if (boot_cpu_has(X86_FEATURE_PER_THREAD_MBA)) |
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r->membw.throttle_mode = THREAD_THROTTLE_PER_THREAD; |
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else |
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r->membw.throttle_mode = THREAD_THROTTLE_MAX; |
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thread_throttle_mode_init(); |
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r->alloc_capable = true; |
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r->alloc_enabled = true; |
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return true; |
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} |
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static bool __rdt_get_mem_config_amd(struct rdt_resource *r) |
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{ |
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struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); |
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union cpuid_0x10_3_eax eax; |
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union cpuid_0x10_x_edx edx; |
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u32 ebx, ecx; |
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cpuid_count(0x80000020, 1, &eax.full, &ebx, &ecx, &edx.full); |
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hw_res->num_closid = edx.split.cos_max + 1; |
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r->default_ctrl = MAX_MBA_BW_AMD; |
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/* AMD does not use delay */ |
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r->membw.delay_linear = false; |
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r->membw.arch_needs_linear = false; |
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/* |
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* AMD does not use memory delay throttle model to control |
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* the allocation like Intel does. |
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*/ |
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r->membw.throttle_mode = THREAD_THROTTLE_UNDEFINED; |
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r->membw.min_bw = 0; |
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r->membw.bw_gran = 1; |
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/* Max value is 2048, Data width should be 4 in decimal */ |
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r->data_width = 4; |
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r->alloc_capable = true; |
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r->alloc_enabled = true; |
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return true; |
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} |
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static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r) |
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{ |
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struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); |
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union cpuid_0x10_1_eax eax; |
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union cpuid_0x10_x_edx edx; |
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u32 ebx, ecx; |
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cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx, &edx.full); |
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hw_res->num_closid = edx.split.cos_max + 1; |
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r->cache.cbm_len = eax.split.cbm_len + 1; |
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r->default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1; |
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r->cache.shareable_bits = ebx & r->default_ctrl; |
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r->data_width = (r->cache.cbm_len + 3) / 4; |
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r->alloc_capable = true; |
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r->alloc_enabled = true; |
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} |
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static void rdt_get_cdp_config(int level) |
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{ |
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/* |
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* By default, CDP is disabled. CDP can be enabled by mount parameter |
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* "cdp" during resctrl file system mount time. |
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*/ |
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rdt_resources_all[level].cdp_enabled = false; |
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rdt_resources_all[level].r_resctrl.cdp_capable = true; |
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} |
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static void rdt_get_cdp_l3_config(void) |
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{ |
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rdt_get_cdp_config(RDT_RESOURCE_L3); |
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} |
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static void rdt_get_cdp_l2_config(void) |
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{ |
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rdt_get_cdp_config(RDT_RESOURCE_L2); |
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} |
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static void |
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mba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r) |
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{ |
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unsigned int i; |
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struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d); |
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struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); |
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for (i = m->low; i < m->high; i++) |
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wrmsrl(hw_res->msr_base + i, hw_dom->ctrl_val[i]); |
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} |
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/* |
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* Map the memory b/w percentage value to delay values |
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* that can be written to QOS_MSRs. |
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* There are currently no SKUs which support non linear delay values. |
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*/ |
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u32 delay_bw_map(unsigned long bw, struct rdt_resource *r) |
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{ |
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if (r->membw.delay_linear) |
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return MAX_MBA_BW - bw; |
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pr_warn_once("Non Linear delay-bw map not supported but queried\n"); |
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return r->default_ctrl; |
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} |
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static void |
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mba_wrmsr_intel(struct rdt_domain *d, struct msr_param *m, |
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struct rdt_resource *r) |
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{ |
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unsigned int i; |
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struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d); |
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struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); |
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/* Write the delay values for mba. */ |
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for (i = m->low; i < m->high; i++) |
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wrmsrl(hw_res->msr_base + i, delay_bw_map(hw_dom->ctrl_val[i], r)); |
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} |
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static void |
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cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r) |
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{ |
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unsigned int i; |
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struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d); |
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struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); |
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for (i = m->low; i < m->high; i++) |
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wrmsrl(hw_res->msr_base + i, hw_dom->ctrl_val[i]); |
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} |
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struct rdt_domain *get_domain_from_cpu(int cpu, struct rdt_resource *r) |
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{ |
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struct rdt_domain *d; |
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list_for_each_entry(d, &r->domains, list) { |
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/* Find the domain that contains this CPU */ |
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if (cpumask_test_cpu(cpu, &d->cpu_mask)) |
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return d; |
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} |
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return NULL; |
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} |
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u32 resctrl_arch_get_num_closid(struct rdt_resource *r) |
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{ |
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return resctrl_to_arch_res(r)->num_closid; |
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} |
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void rdt_ctrl_update(void *arg) |
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{ |
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struct msr_param *m = arg; |
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struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res); |
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struct rdt_resource *r = m->res; |
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int cpu = smp_processor_id(); |
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struct rdt_domain *d; |
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d = get_domain_from_cpu(cpu, r); |
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if (d) { |
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hw_res->msr_update(d, m, r); |
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return; |
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} |
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pr_warn_once("cpu %d not found in any domain for resource %s\n", |
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cpu, r->name); |
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} |
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/* |
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* rdt_find_domain - Find a domain in a resource that matches input resource id |
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* |
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* Search resource r's domain list to find the resource id. If the resource |
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* id is found in a domain, return the domain. Otherwise, if requested by |
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* caller, return the first domain whose id is bigger than the input id. |
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* The domain list is sorted by id in ascending order. |
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*/ |
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struct rdt_domain *rdt_find_domain(struct rdt_resource *r, int id, |
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struct list_head **pos) |
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{ |
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struct rdt_domain *d; |
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struct list_head *l; |
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if (id < 0) |
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return ERR_PTR(-ENODEV); |
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list_for_each(l, &r->domains) { |
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d = list_entry(l, struct rdt_domain, list); |
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/* When id is found, return its domain. */ |
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if (id == d->id) |
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return d; |
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/* Stop searching when finding id's position in sorted list. */ |
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if (id < d->id) |
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break; |
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} |
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if (pos) |
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*pos = l; |
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return NULL; |
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} |
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void setup_default_ctrlval(struct rdt_resource *r, u32 *dc, u32 *dm) |
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{ |
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struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); |
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int i; |
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/* |
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* Initialize the Control MSRs to having no control. |
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* For Cache Allocation: Set all bits in cbm |
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* For Memory Allocation: Set b/w requested to 100% |
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* and the bandwidth in MBps to U32_MAX |
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*/ |
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for (i = 0; i < hw_res->num_closid; i++, dc++, dm++) { |
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*dc = r->default_ctrl; |
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*dm = MBA_MAX_MBPS; |
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} |
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} |
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static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_domain *d) |
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{ |
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struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); |
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struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d); |
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struct msr_param m; |
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u32 *dc, *dm; |
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dc = kmalloc_array(hw_res->num_closid, sizeof(*hw_dom->ctrl_val), |
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GFP_KERNEL); |
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if (!dc) |
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return -ENOMEM; |
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dm = kmalloc_array(hw_res->num_closid, sizeof(*hw_dom->mbps_val), |
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GFP_KERNEL); |
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if (!dm) { |
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kfree(dc); |
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return -ENOMEM; |
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} |
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hw_dom->ctrl_val = dc; |
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hw_dom->mbps_val = dm; |
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setup_default_ctrlval(r, dc, dm); |
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m.low = 0; |
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m.high = hw_res->num_closid; |
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hw_res->msr_update(d, &m, r); |
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return 0; |
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} |
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static int domain_setup_mon_state(struct rdt_resource *r, struct rdt_domain *d) |
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{ |
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size_t tsize; |
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if (is_llc_occupancy_enabled()) { |
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d->rmid_busy_llc = bitmap_zalloc(r->num_rmid, GFP_KERNEL); |
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if (!d->rmid_busy_llc) |
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return -ENOMEM; |
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INIT_DELAYED_WORK(&d->cqm_limbo, cqm_handle_limbo); |
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} |
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if (is_mbm_total_enabled()) { |
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tsize = sizeof(*d->mbm_total); |
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d->mbm_total = kcalloc(r->num_rmid, tsize, GFP_KERNEL); |
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if (!d->mbm_total) { |
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bitmap_free(d->rmid_busy_llc); |
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return -ENOMEM; |
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} |
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} |
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if (is_mbm_local_enabled()) { |
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tsize = sizeof(*d->mbm_local); |
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d->mbm_local = kcalloc(r->num_rmid, tsize, GFP_KERNEL); |
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if (!d->mbm_local) { |
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bitmap_free(d->rmid_busy_llc); |
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kfree(d->mbm_total); |
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return -ENOMEM; |
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} |
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} |
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if (is_mbm_enabled()) { |
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INIT_DELAYED_WORK(&d->mbm_over, mbm_handle_overflow); |
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mbm_setup_overflow_handler(d, MBM_OVERFLOW_INTERVAL); |
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} |
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return 0; |
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} |
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|
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/* |
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* domain_add_cpu - Add a cpu to a resource's domain list. |
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* |
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* If an existing domain in the resource r's domain list matches the cpu's |
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* resource id, add the cpu in the domain. |
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* |
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* Otherwise, a new domain is allocated and inserted into the right position |
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* in the domain list sorted by id in ascending order. |
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* |
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* The order in the domain list is visible to users when we print entries |
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* in the schemata file and schemata input is validated to have the same order |
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* as this list. |
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*/ |
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static void domain_add_cpu(int cpu, struct rdt_resource *r) |
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{ |
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int id = get_cpu_cacheinfo_id(cpu, r->cache_level); |
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struct list_head *add_pos = NULL; |
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struct rdt_hw_domain *hw_dom; |
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struct rdt_domain *d; |
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d = rdt_find_domain(r, id, &add_pos); |
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if (IS_ERR(d)) { |
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pr_warn("Couldn't find cache id for CPU %d\n", cpu); |
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return; |
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} |
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if (d) { |
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cpumask_set_cpu(cpu, &d->cpu_mask); |
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if (r->cache.arch_has_per_cpu_cfg) |
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rdt_domain_reconfigure_cdp(r); |
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return; |
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} |
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hw_dom = kzalloc_node(sizeof(*hw_dom), GFP_KERNEL, cpu_to_node(cpu)); |
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if (!hw_dom) |
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return; |
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d = &hw_dom->d_resctrl; |
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d->id = id; |
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cpumask_set_cpu(cpu, &d->cpu_mask); |
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|
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rdt_domain_reconfigure_cdp(r); |
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if (r->alloc_capable && domain_setup_ctrlval(r, d)) { |
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kfree(hw_dom); |
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return; |
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} |
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|
|
if (r->mon_capable && domain_setup_mon_state(r, d)) { |
|
kfree(hw_dom->ctrl_val); |
|
kfree(hw_dom->mbps_val); |
|
kfree(hw_dom); |
|
return; |
|
} |
|
|
|
list_add_tail(&d->list, add_pos); |
|
|
|
/* |
|
* If resctrl is mounted, add |
|
* per domain monitor data directories. |
|
*/ |
|
if (static_branch_unlikely(&rdt_mon_enable_key)) |
|
mkdir_mondata_subdir_allrdtgrp(r, d); |
|
} |
|
|
|
static void domain_remove_cpu(int cpu, struct rdt_resource *r) |
|
{ |
|
int id = get_cpu_cacheinfo_id(cpu, r->cache_level); |
|
struct rdt_hw_domain *hw_dom; |
|
struct rdt_domain *d; |
|
|
|
d = rdt_find_domain(r, id, NULL); |
|
if (IS_ERR_OR_NULL(d)) { |
|
pr_warn("Couldn't find cache id for CPU %d\n", cpu); |
|
return; |
|
} |
|
hw_dom = resctrl_to_arch_dom(d); |
|
|
|
cpumask_clear_cpu(cpu, &d->cpu_mask); |
|
if (cpumask_empty(&d->cpu_mask)) { |
|
/* |
|
* If resctrl is mounted, remove all the |
|
* per domain monitor data directories. |
|
*/ |
|
if (static_branch_unlikely(&rdt_mon_enable_key)) |
|
rmdir_mondata_subdir_allrdtgrp(r, d->id); |
|
list_del(&d->list); |
|
if (r->mon_capable && is_mbm_enabled()) |
|
cancel_delayed_work(&d->mbm_over); |
|
if (is_llc_occupancy_enabled() && has_busy_rmid(r, d)) { |
|
/* |
|
* When a package is going down, forcefully |
|
* decrement rmid->ebusy. There is no way to know |
|
* that the L3 was flushed and hence may lead to |
|
* incorrect counts in rare scenarios, but leaving |
|
* the RMID as busy creates RMID leaks if the |
|
* package never comes back. |
|
*/ |
|
__check_limbo(d, true); |
|
cancel_delayed_work(&d->cqm_limbo); |
|
} |
|
|
|
/* |
|
* rdt_domain "d" is going to be freed below, so clear |
|
* its pointer from pseudo_lock_region struct. |
|
*/ |
|
if (d->plr) |
|
d->plr->d = NULL; |
|
|
|
kfree(hw_dom->ctrl_val); |
|
kfree(hw_dom->mbps_val); |
|
bitmap_free(d->rmid_busy_llc); |
|
kfree(d->mbm_total); |
|
kfree(d->mbm_local); |
|
kfree(hw_dom); |
|
return; |
|
} |
|
|
|
if (r == &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl) { |
|
if (is_mbm_enabled() && cpu == d->mbm_work_cpu) { |
|
cancel_delayed_work(&d->mbm_over); |
|
mbm_setup_overflow_handler(d, 0); |
|
} |
|
if (is_llc_occupancy_enabled() && cpu == d->cqm_work_cpu && |
|
has_busy_rmid(r, d)) { |
|
cancel_delayed_work(&d->cqm_limbo); |
|
cqm_setup_limbo_handler(d, 0); |
|
} |
|
} |
|
} |
|
|
|
static void clear_closid_rmid(int cpu) |
|
{ |
|
struct resctrl_pqr_state *state = this_cpu_ptr(&pqr_state); |
|
|
|
state->default_closid = 0; |
|
state->default_rmid = 0; |
|
state->cur_closid = 0; |
|
state->cur_rmid = 0; |
|
wrmsr(IA32_PQR_ASSOC, 0, 0); |
|
} |
|
|
|
static int resctrl_online_cpu(unsigned int cpu) |
|
{ |
|
struct rdt_resource *r; |
|
|
|
mutex_lock(&rdtgroup_mutex); |
|
for_each_capable_rdt_resource(r) |
|
domain_add_cpu(cpu, r); |
|
/* The cpu is set in default rdtgroup after online. */ |
|
cpumask_set_cpu(cpu, &rdtgroup_default.cpu_mask); |
|
clear_closid_rmid(cpu); |
|
mutex_unlock(&rdtgroup_mutex); |
|
|
|
return 0; |
|
} |
|
|
|
static void clear_childcpus(struct rdtgroup *r, unsigned int cpu) |
|
{ |
|
struct rdtgroup *cr; |
|
|
|
list_for_each_entry(cr, &r->mon.crdtgrp_list, mon.crdtgrp_list) { |
|
if (cpumask_test_and_clear_cpu(cpu, &cr->cpu_mask)) { |
|
break; |
|
} |
|
} |
|
} |
|
|
|
static int resctrl_offline_cpu(unsigned int cpu) |
|
{ |
|
struct rdtgroup *rdtgrp; |
|
struct rdt_resource *r; |
|
|
|
mutex_lock(&rdtgroup_mutex); |
|
for_each_capable_rdt_resource(r) |
|
domain_remove_cpu(cpu, r); |
|
list_for_each_entry(rdtgrp, &rdt_all_groups, rdtgroup_list) { |
|
if (cpumask_test_and_clear_cpu(cpu, &rdtgrp->cpu_mask)) { |
|
clear_childcpus(rdtgrp, cpu); |
|
break; |
|
} |
|
} |
|
clear_closid_rmid(cpu); |
|
mutex_unlock(&rdtgroup_mutex); |
|
|
|
return 0; |
|
} |
|
|
|
/* |
|
* Choose a width for the resource name and resource data based on the |
|
* resource that has widest name and cbm. |
|
*/ |
|
static __init void rdt_init_padding(void) |
|
{ |
|
struct rdt_resource *r; |
|
|
|
for_each_alloc_capable_rdt_resource(r) { |
|
if (r->data_width > max_data_width) |
|
max_data_width = r->data_width; |
|
} |
|
} |
|
|
|
enum { |
|
RDT_FLAG_CMT, |
|
RDT_FLAG_MBM_TOTAL, |
|
RDT_FLAG_MBM_LOCAL, |
|
RDT_FLAG_L3_CAT, |
|
RDT_FLAG_L3_CDP, |
|
RDT_FLAG_L2_CAT, |
|
RDT_FLAG_L2_CDP, |
|
RDT_FLAG_MBA, |
|
}; |
|
|
|
#define RDT_OPT(idx, n, f) \ |
|
[idx] = { \ |
|
.name = n, \ |
|
.flag = f \ |
|
} |
|
|
|
struct rdt_options { |
|
char *name; |
|
int flag; |
|
bool force_off, force_on; |
|
}; |
|
|
|
static struct rdt_options rdt_options[] __initdata = { |
|
RDT_OPT(RDT_FLAG_CMT, "cmt", X86_FEATURE_CQM_OCCUP_LLC), |
|
RDT_OPT(RDT_FLAG_MBM_TOTAL, "mbmtotal", X86_FEATURE_CQM_MBM_TOTAL), |
|
RDT_OPT(RDT_FLAG_MBM_LOCAL, "mbmlocal", X86_FEATURE_CQM_MBM_LOCAL), |
|
RDT_OPT(RDT_FLAG_L3_CAT, "l3cat", X86_FEATURE_CAT_L3), |
|
RDT_OPT(RDT_FLAG_L3_CDP, "l3cdp", X86_FEATURE_CDP_L3), |
|
RDT_OPT(RDT_FLAG_L2_CAT, "l2cat", X86_FEATURE_CAT_L2), |
|
RDT_OPT(RDT_FLAG_L2_CDP, "l2cdp", X86_FEATURE_CDP_L2), |
|
RDT_OPT(RDT_FLAG_MBA, "mba", X86_FEATURE_MBA), |
|
}; |
|
#define NUM_RDT_OPTIONS ARRAY_SIZE(rdt_options) |
|
|
|
static int __init set_rdt_options(char *str) |
|
{ |
|
struct rdt_options *o; |
|
bool force_off; |
|
char *tok; |
|
|
|
if (*str == '=') |
|
str++; |
|
while ((tok = strsep(&str, ",")) != NULL) { |
|
force_off = *tok == '!'; |
|
if (force_off) |
|
tok++; |
|
for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) { |
|
if (strcmp(tok, o->name) == 0) { |
|
if (force_off) |
|
o->force_off = true; |
|
else |
|
o->force_on = true; |
|
break; |
|
} |
|
} |
|
} |
|
return 1; |
|
} |
|
__setup("rdt", set_rdt_options); |
|
|
|
static bool __init rdt_cpu_has(int flag) |
|
{ |
|
bool ret = boot_cpu_has(flag); |
|
struct rdt_options *o; |
|
|
|
if (!ret) |
|
return ret; |
|
|
|
for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) { |
|
if (flag == o->flag) { |
|
if (o->force_off) |
|
ret = false; |
|
if (o->force_on) |
|
ret = true; |
|
break; |
|
} |
|
} |
|
return ret; |
|
} |
|
|
|
static __init bool get_mem_config(void) |
|
{ |
|
struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_MBA]; |
|
|
|
if (!rdt_cpu_has(X86_FEATURE_MBA)) |
|
return false; |
|
|
|
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
|
return __get_mem_config_intel(&hw_res->r_resctrl); |
|
else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
|
return __rdt_get_mem_config_amd(&hw_res->r_resctrl); |
|
|
|
return false; |
|
} |
|
|
|
static __init bool get_rdt_alloc_resources(void) |
|
{ |
|
struct rdt_resource *r; |
|
bool ret = false; |
|
|
|
if (rdt_alloc_capable) |
|
return true; |
|
|
|
if (!boot_cpu_has(X86_FEATURE_RDT_A)) |
|
return false; |
|
|
|
if (rdt_cpu_has(X86_FEATURE_CAT_L3)) { |
|
r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; |
|
rdt_get_cache_alloc_cfg(1, r); |
|
if (rdt_cpu_has(X86_FEATURE_CDP_L3)) |
|
rdt_get_cdp_l3_config(); |
|
ret = true; |
|
} |
|
if (rdt_cpu_has(X86_FEATURE_CAT_L2)) { |
|
/* CPUID 0x10.2 fields are same format at 0x10.1 */ |
|
r = &rdt_resources_all[RDT_RESOURCE_L2].r_resctrl; |
|
rdt_get_cache_alloc_cfg(2, r); |
|
if (rdt_cpu_has(X86_FEATURE_CDP_L2)) |
|
rdt_get_cdp_l2_config(); |
|
ret = true; |
|
} |
|
|
|
if (get_mem_config()) |
|
ret = true; |
|
|
|
return ret; |
|
} |
|
|
|
static __init bool get_rdt_mon_resources(void) |
|
{ |
|
struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; |
|
|
|
if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) |
|
rdt_mon_features |= (1 << QOS_L3_OCCUP_EVENT_ID); |
|
if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) |
|
rdt_mon_features |= (1 << QOS_L3_MBM_TOTAL_EVENT_ID); |
|
if (rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL)) |
|
rdt_mon_features |= (1 << QOS_L3_MBM_LOCAL_EVENT_ID); |
|
|
|
if (!rdt_mon_features) |
|
return false; |
|
|
|
return !rdt_get_mon_l3_config(r); |
|
} |
|
|
|
static __init void __check_quirks_intel(void) |
|
{ |
|
switch (boot_cpu_data.x86_model) { |
|
case INTEL_FAM6_HASWELL_X: |
|
if (!rdt_options[RDT_FLAG_L3_CAT].force_off) |
|
cache_alloc_hsw_probe(); |
|
break; |
|
case INTEL_FAM6_SKYLAKE_X: |
|
if (boot_cpu_data.x86_stepping <= 4) |
|
set_rdt_options("!cmt,!mbmtotal,!mbmlocal,!l3cat"); |
|
else |
|
set_rdt_options("!l3cat"); |
|
fallthrough; |
|
case INTEL_FAM6_BROADWELL_X: |
|
intel_rdt_mbm_apply_quirk(); |
|
break; |
|
} |
|
} |
|
|
|
static __init void check_quirks(void) |
|
{ |
|
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
|
__check_quirks_intel(); |
|
} |
|
|
|
static __init bool get_rdt_resources(void) |
|
{ |
|
rdt_alloc_capable = get_rdt_alloc_resources(); |
|
rdt_mon_capable = get_rdt_mon_resources(); |
|
|
|
return (rdt_mon_capable || rdt_alloc_capable); |
|
} |
|
|
|
static __init void rdt_init_res_defs_intel(void) |
|
{ |
|
struct rdt_hw_resource *hw_res; |
|
struct rdt_resource *r; |
|
|
|
for_each_rdt_resource(r) { |
|
hw_res = resctrl_to_arch_res(r); |
|
|
|
if (r->rid == RDT_RESOURCE_L3 || |
|
r->rid == RDT_RESOURCE_L2) { |
|
r->cache.arch_has_sparse_bitmaps = false; |
|
r->cache.arch_has_empty_bitmaps = false; |
|
r->cache.arch_has_per_cpu_cfg = false; |
|
} else if (r->rid == RDT_RESOURCE_MBA) { |
|
hw_res->msr_base = MSR_IA32_MBA_THRTL_BASE; |
|
hw_res->msr_update = mba_wrmsr_intel; |
|
} |
|
} |
|
} |
|
|
|
static __init void rdt_init_res_defs_amd(void) |
|
{ |
|
struct rdt_hw_resource *hw_res; |
|
struct rdt_resource *r; |
|
|
|
for_each_rdt_resource(r) { |
|
hw_res = resctrl_to_arch_res(r); |
|
|
|
if (r->rid == RDT_RESOURCE_L3 || |
|
r->rid == RDT_RESOURCE_L2) { |
|
r->cache.arch_has_sparse_bitmaps = true; |
|
r->cache.arch_has_empty_bitmaps = true; |
|
r->cache.arch_has_per_cpu_cfg = true; |
|
} else if (r->rid == RDT_RESOURCE_MBA) { |
|
hw_res->msr_base = MSR_IA32_MBA_BW_BASE; |
|
hw_res->msr_update = mba_wrmsr_amd; |
|
} |
|
} |
|
} |
|
|
|
static __init void rdt_init_res_defs(void) |
|
{ |
|
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
|
rdt_init_res_defs_intel(); |
|
else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
|
rdt_init_res_defs_amd(); |
|
} |
|
|
|
static enum cpuhp_state rdt_online; |
|
|
|
/* Runs once on the BSP during boot. */ |
|
void resctrl_cpu_detect(struct cpuinfo_x86 *c) |
|
{ |
|
if (!cpu_has(c, X86_FEATURE_CQM_LLC)) { |
|
c->x86_cache_max_rmid = -1; |
|
c->x86_cache_occ_scale = -1; |
|
c->x86_cache_mbm_width_offset = -1; |
|
return; |
|
} |
|
|
|
/* will be overridden if occupancy monitoring exists */ |
|
c->x86_cache_max_rmid = cpuid_ebx(0xf); |
|
|
|
if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) || |
|
cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) || |
|
cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) { |
|
u32 eax, ebx, ecx, edx; |
|
|
|
/* QoS sub-leaf, EAX=0Fh, ECX=1 */ |
|
cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx); |
|
|
|
c->x86_cache_max_rmid = ecx; |
|
c->x86_cache_occ_scale = ebx; |
|
c->x86_cache_mbm_width_offset = eax & 0xff; |
|
|
|
if (c->x86_vendor == X86_VENDOR_AMD && !c->x86_cache_mbm_width_offset) |
|
c->x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_AMD; |
|
} |
|
} |
|
|
|
static int __init resctrl_late_init(void) |
|
{ |
|
struct rdt_resource *r; |
|
int state, ret; |
|
|
|
/* |
|
* Initialize functions(or definitions) that are different |
|
* between vendors here. |
|
*/ |
|
rdt_init_res_defs(); |
|
|
|
check_quirks(); |
|
|
|
if (!get_rdt_resources()) |
|
return -ENODEV; |
|
|
|
rdt_init_padding(); |
|
|
|
state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, |
|
"x86/resctrl/cat:online:", |
|
resctrl_online_cpu, resctrl_offline_cpu); |
|
if (state < 0) |
|
return state; |
|
|
|
ret = rdtgroup_init(); |
|
if (ret) { |
|
cpuhp_remove_state(state); |
|
return ret; |
|
} |
|
rdt_online = state; |
|
|
|
for_each_alloc_capable_rdt_resource(r) |
|
pr_info("%s allocation detected\n", r->name); |
|
|
|
for_each_mon_capable_rdt_resource(r) |
|
pr_info("%s monitoring detected\n", r->name); |
|
|
|
return 0; |
|
} |
|
|
|
late_initcall(resctrl_late_init); |
|
|
|
static void __exit resctrl_exit(void) |
|
{ |
|
cpuhp_remove_state(rdt_online); |
|
rdtgroup_exit(); |
|
} |
|
|
|
__exitcall(resctrl_exit);
|
|
|