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98 lines
3.2 KiB
98 lines
3.2 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef __ASM_SH_SE7722_H |
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#define __ASM_SH_SE7722_H |
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/* |
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* linux/include/asm-sh/se7722.h |
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* |
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* Copyright (C) 2007 Nobuhiro Iwamatsu |
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* |
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* Hitachi UL SolutionEngine 7722 Support. |
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*/ |
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#include <linux/sh_intc.h> |
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#include <asm/addrspace.h> |
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/* Box specific addresses. */ |
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#define SE_AREA0_WIDTH 4 /* Area0: 32bit */ |
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#define PA_ROM 0xa0000000 /* EPROM */ |
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#define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */ |
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#define PA_FROM 0xa1000000 /* Flash-ROM */ |
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#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */ |
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#define PA_EXT1 0xa4000000 |
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#define PA_EXT1_SIZE 0x04000000 |
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#define PA_SDRAM 0xaC000000 /* DDR-SDRAM(Area3) 64MB */ |
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#define PA_SDRAM_SIZE 0x04000000 |
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#define PA_EXT4 0xb0000000 |
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#define PA_EXT4_SIZE 0x04000000 |
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#define PA_PERIPHERAL 0xB0000000 |
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#define PA_PCIC PA_PERIPHERAL /* MR-SHPC-01 PCMCIA */ |
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#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) /* MR-SHPC-01 PCMCIA controller */ |
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#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) /* MR-SHPC-01 memory window base */ |
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#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) /* MR-SHPC-01 attribute window base */ |
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#define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000) /* MR-SHPC-01 I/O window base */ |
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#define MRSHPC_OPTION (PA_MRSHPC + 6) |
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#define MRSHPC_CSR (PA_MRSHPC + 8) |
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#define MRSHPC_ISR (PA_MRSHPC + 10) |
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#define MRSHPC_ICR (PA_MRSHPC + 12) |
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#define MRSHPC_CPWCR (PA_MRSHPC + 14) |
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#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) |
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#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) |
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#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) |
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#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) |
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#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) |
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#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) |
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#define MRSHPC_CDCR (PA_MRSHPC + 28) |
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#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) |
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#define PA_LED (PA_PERIPHERAL + 0x00800000) /* 8bit LED */ |
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#define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */ |
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#define PA_LAN (PA_AREA6_IO + 0) /* SMC LAN91C111 */ |
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/* GPIO */ |
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#define FPGA_IN 0xb1840000UL |
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#define FPGA_OUT 0xb1840004UL |
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#define PORT_PECR 0xA4050108UL |
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#define PORT_PJCR 0xA4050110UL |
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#define PORT_PSELD 0xA4050154UL |
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#define PORT_PSELB 0xA4050150UL |
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#define PORT_PSELC 0xA4050152UL |
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#define PORT_PKCR 0xA4050112UL |
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#define PORT_PHCR 0xA405010EUL |
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#define PORT_PLCR 0xA4050114UL |
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#define PORT_PMCR 0xA4050116UL |
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#define PORT_PRCR 0xA405011CUL |
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#define PORT_PXCR 0xA4050148UL |
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#define PORT_PSELA 0xA405014EUL |
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#define PORT_PYCR 0xA405014AUL |
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#define PORT_PZCR 0xA405014CUL |
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#define PORT_HIZCRA 0xA4050158UL |
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#define PORT_HIZCRC 0xA405015CUL |
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/* IRQ */ |
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#define IRQ0_IRQ evt2irq(0x600) |
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#define IRQ1_IRQ evt2irq(0x620) |
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#define SE7722_FPGA_IRQ_USB 0 /* IRQ0 */ |
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#define SE7722_FPGA_IRQ_SMC 1 /* IRQ0 */ |
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#define SE7722_FPGA_IRQ_MRSHPC0 2 /* IRQ1 */ |
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#define SE7722_FPGA_IRQ_MRSHPC1 3 /* IRQ1 */ |
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#define SE7722_FPGA_IRQ_MRSHPC2 4 /* IRQ1 */ |
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#define SE7722_FPGA_IRQ_MRSHPC3 5 /* IRQ1 */ |
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#define SE7722_FPGA_IRQ_NR 6 |
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struct irq_domain; |
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/* arch/sh/boards/se/7722/irq.c */ |
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extern struct irq_domain *se7722_irq_domain; |
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void init_se7722_IRQ(void); |
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#define __IO_PREFIX se7722 |
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#include <asm/io_generic.h> |
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#endif /* __ASM_SH_SE7722_H */
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