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79 lines
1.9 KiB
79 lines
1.9 KiB
/* SPDX-License-Identifier: GPL-2.0 |
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* |
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* include/asm-sh/cpu-sh4/mmu_context.h |
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* |
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* Copyright (C) 1999 Niibe Yutaka |
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*/ |
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#ifndef __ASM_CPU_SH4_MMU_CONTEXT_H |
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#define __ASM_CPU_SH4_MMU_CONTEXT_H |
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#define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */ |
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#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */ |
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#define MMU_TTB 0xFF000008 /* Translation table base register */ |
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#define MMU_TEA 0xFF00000C /* TLB Exception Address */ |
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#define MMU_PTEA 0xFF000034 /* PTE assistance register */ |
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#define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */ |
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#define MMUCR 0xFF000010 /* MMU Control Register */ |
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#define MMU_TLB_ENTRY_SHIFT 8 |
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#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000 |
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#define MMU_ITLB_ADDRESS_ARRAY2 0xF2800000 |
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#define MMU_ITLB_DATA_ARRAY 0xF3000000 |
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#define MMU_ITLB_DATA_ARRAY2 0xF3800000 |
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#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000 |
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#define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000 |
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#define MMU_UTLB_DATA_ARRAY 0xF7000000 |
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#define MMU_UTLB_DATA_ARRAY2 0xF7800000 |
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#define MMU_PAGE_ASSOC_BIT 0x80 |
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#ifdef CONFIG_MMU |
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#define MMUCR_AT (1 << 0) |
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#else |
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#define MMUCR_AT (0) |
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#endif |
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#define MMUCR_TI (1 << 2) |
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#define MMUCR_URB 0x00FC0000 |
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#define MMUCR_URB_SHIFT 18 |
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#define MMUCR_URB_NENTRIES 64 |
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#define MMUCR_URC 0x0000FC00 |
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#define MMUCR_URC_SHIFT 10 |
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#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40) |
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#define MMUCR_SE (1 << 4) |
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#else |
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#define MMUCR_SE (0) |
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#endif |
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#ifdef CONFIG_CPU_HAS_PTEAEX |
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#define MMUCR_AEX (1 << 6) |
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#else |
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#define MMUCR_AEX (0) |
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#endif |
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#ifdef CONFIG_X2TLB |
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#define MMUCR_ME (1 << 7) |
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#else |
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#define MMUCR_ME (0) |
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#endif |
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#ifdef CONFIG_SH_STORE_QUEUES |
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#define MMUCR_SQMD (1 << 9) |
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#else |
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#define MMUCR_SQMD (0) |
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#endif |
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#define MMU_NTLB_ENTRIES 64 |
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#define MMU_CONTROL_INIT (MMUCR_AT | MMUCR_TI | MMUCR_SQMD | \ |
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MMUCR_ME | MMUCR_SE | MMUCR_AEX) |
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#define TRA 0xff000020 |
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#define EXPEVT 0xff000024 |
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#define INTEVT 0xff000028 |
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#endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */ |
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