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159 lines
3.9 KiB
159 lines
3.9 KiB
/* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* include/asm-sh/watchdog.h |
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* |
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* Copyright (C) 2002, 2003 Paul Mundt |
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* Copyright (C) 2009 Siemens AG |
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* Copyright (C) 2009 Valentin Sitdikov |
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*/ |
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#ifndef __ASM_SH_WATCHDOG_H |
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#define __ASM_SH_WATCHDOG_H |
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#include <linux/types.h> |
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#include <linux/io.h> |
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#define WTCNT_HIGH 0x5a |
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#define WTCSR_HIGH 0xa5 |
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#define WTCSR_CKS2 0x04 |
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#define WTCSR_CKS1 0x02 |
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#define WTCSR_CKS0 0x01 |
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#include <cpu/watchdog.h> |
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/* |
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* See cpu-sh2/watchdog.h for explanation of this stupidity.. |
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*/ |
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#ifndef WTCNT_R |
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# define WTCNT_R WTCNT |
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#endif |
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#ifndef WTCSR_R |
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# define WTCSR_R WTCSR |
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#endif |
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/* |
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* CKS0-2 supports a number of clock division ratios. At the time the watchdog |
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* is enabled, it defaults to a 41 usec overflow period .. we overload this to |
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* something a little more reasonable, and really can't deal with anything |
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* lower than WTCSR_CKS_1024, else we drop back into the usec range. |
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* |
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* Clock Division Ratio Overflow Period |
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* -------------------------------------------- |
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* 1/32 (initial value) 41 usecs |
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* 1/64 82 usecs |
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* 1/128 164 usecs |
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* 1/256 328 usecs |
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* 1/512 656 usecs |
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* 1/1024 1.31 msecs |
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* 1/2048 2.62 msecs |
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* 1/4096 5.25 msecs |
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*/ |
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#define WTCSR_CKS_32 0x00 |
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#define WTCSR_CKS_64 0x01 |
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#define WTCSR_CKS_128 0x02 |
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#define WTCSR_CKS_256 0x03 |
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#define WTCSR_CKS_512 0x04 |
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#define WTCSR_CKS_1024 0x05 |
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#define WTCSR_CKS_2048 0x06 |
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#define WTCSR_CKS_4096 0x07 |
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#if defined(CONFIG_CPU_SUBTYPE_SH7785) || defined(CONFIG_CPU_SUBTYPE_SH7780) |
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/** |
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* sh_wdt_read_cnt - Read from Counter |
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* Reads back the WTCNT value. |
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*/ |
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static inline __u32 sh_wdt_read_cnt(void) |
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{ |
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return __raw_readl(WTCNT_R); |
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} |
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/** |
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* sh_wdt_write_cnt - Write to Counter |
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* @val: Value to write |
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* |
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* Writes the given value @val to the lower byte of the timer counter. |
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* The upper byte is set manually on each write. |
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*/ |
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static inline void sh_wdt_write_cnt(__u32 val) |
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{ |
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__raw_writel((WTCNT_HIGH << 24) | (__u32)val, WTCNT); |
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} |
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/** |
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* sh_wdt_write_bst - Write to Counter |
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* @val: Value to write |
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* |
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* Writes the given value @val to the lower byte of the timer counter. |
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* The upper byte is set manually on each write. |
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*/ |
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static inline void sh_wdt_write_bst(__u32 val) |
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{ |
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__raw_writel((WTBST_HIGH << 24) | (__u32)val, WTBST); |
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} |
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/** |
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* sh_wdt_read_csr - Read from Control/Status Register |
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* |
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* Reads back the WTCSR value. |
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*/ |
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static inline __u32 sh_wdt_read_csr(void) |
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{ |
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return __raw_readl(WTCSR_R); |
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} |
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/** |
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* sh_wdt_write_csr - Write to Control/Status Register |
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* @val: Value to write |
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* |
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* Writes the given value @val to the lower byte of the control/status |
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* register. The upper byte is set manually on each write. |
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*/ |
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static inline void sh_wdt_write_csr(__u32 val) |
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{ |
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__raw_writel((WTCSR_HIGH << 24) | (__u32)val, WTCSR); |
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} |
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#else |
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/** |
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* sh_wdt_read_cnt - Read from Counter |
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* Reads back the WTCNT value. |
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*/ |
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static inline __u8 sh_wdt_read_cnt(void) |
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{ |
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return __raw_readb(WTCNT_R); |
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} |
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/** |
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* sh_wdt_write_cnt - Write to Counter |
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* @val: Value to write |
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* |
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* Writes the given value @val to the lower byte of the timer counter. |
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* The upper byte is set manually on each write. |
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*/ |
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static inline void sh_wdt_write_cnt(__u8 val) |
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{ |
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__raw_writew((WTCNT_HIGH << 8) | (__u16)val, WTCNT); |
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} |
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/** |
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* sh_wdt_read_csr - Read from Control/Status Register |
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* |
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* Reads back the WTCSR value. |
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*/ |
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static inline __u8 sh_wdt_read_csr(void) |
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{ |
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return __raw_readb(WTCSR_R); |
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} |
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/** |
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* sh_wdt_write_csr - Write to Control/Status Register |
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* @val: Value to write |
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* |
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* Writes the given value @val to the lower byte of the control/status |
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* register. The upper byte is set manually on each write. |
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*/ |
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static inline void sh_wdt_write_csr(__u8 val) |
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{ |
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__raw_writew((WTCSR_HIGH << 8) | (__u16)val, WTCSR); |
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} |
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#endif /* CONFIG_CPU_SUBTYPE_SH7785 || CONFIG_CPU_SUBTYPE_SH7780 */ |
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#endif /* __ASM_SH_WATCHDOG_H */
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