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105 lines
2.3 KiB
105 lines
2.3 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Generic SH-4 / SH-4A PCIC operations (SH7751, SH7780). |
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* |
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* Copyright (C) 2002 - 2009 Paul Mundt |
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*/ |
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#include <linux/pci.h> |
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#include <linux/io.h> |
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#include <linux/spinlock.h> |
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#include <asm/addrspace.h> |
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#include "pci-sh4.h" |
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/* |
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* Direct access to PCI hardware... |
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*/ |
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#define CONFIG_CMD(bus, devfn, where) \ |
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(0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3)) |
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/* |
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* Functions for accessing PCI configuration space with type 1 accesses |
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*/ |
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static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 *val) |
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{ |
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struct pci_channel *chan = bus->sysdata; |
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unsigned long flags; |
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u32 data; |
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/* |
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* PCIPDR may only be accessed as 32 bit words, |
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* so we must do byte alignment by hand |
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*/ |
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raw_spin_lock_irqsave(&pci_config_lock, flags); |
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pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR); |
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data = pci_read_reg(chan, SH4_PCIPDR); |
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raw_spin_unlock_irqrestore(&pci_config_lock, flags); |
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switch (size) { |
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case 1: |
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*val = (data >> ((where & 3) << 3)) & 0xff; |
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break; |
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case 2: |
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*val = (data >> ((where & 2) << 3)) & 0xffff; |
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break; |
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case 4: |
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*val = data; |
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break; |
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default: |
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return PCIBIOS_FUNC_NOT_SUPPORTED; |
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} |
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return PCIBIOS_SUCCESSFUL; |
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} |
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/* |
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* Since SH4 only does 32bit access we'll have to do a read, |
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* mask,write operation. |
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* We'll allow an odd byte offset, though it should be illegal. |
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*/ |
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static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 val) |
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{ |
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struct pci_channel *chan = bus->sysdata; |
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unsigned long flags; |
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int shift; |
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u32 data; |
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raw_spin_lock_irqsave(&pci_config_lock, flags); |
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pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR); |
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data = pci_read_reg(chan, SH4_PCIPDR); |
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raw_spin_unlock_irqrestore(&pci_config_lock, flags); |
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switch (size) { |
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case 1: |
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shift = (where & 3) << 3; |
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data &= ~(0xff << shift); |
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data |= ((val & 0xff) << shift); |
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break; |
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case 2: |
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shift = (where & 2) << 3; |
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data &= ~(0xffff << shift); |
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data |= ((val & 0xffff) << shift); |
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break; |
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case 4: |
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data = val; |
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break; |
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default: |
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return PCIBIOS_FUNC_NOT_SUPPORTED; |
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} |
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pci_write_reg(chan, data, SH4_PCIPDR); |
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return PCIBIOS_SUCCESSFUL; |
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} |
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struct pci_ops sh4_pci_ops = { |
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.read = sh4_pci_read, |
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.write = sh4_pci_write, |
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}; |
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int __attribute__((weak)) pci_fixup_pcic(struct pci_channel *chan) |
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{ |
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/* Nothing to do. */ |
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return 0; |
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}
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