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485 lines
11 KiB
485 lines
11 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright (C) 2008 Thomas Gleixner <[email protected]> |
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* Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar |
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* Copyright (C) 2009 Jaswinder Singh Rajput |
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* Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter |
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* Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra |
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* Copyright (C) 2009 Intel Corporation, <[email protected]> |
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* Copyright (C) 2009 Google, Inc., Stephane Eranian |
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* Copyright 2014 Tilera Corporation. All Rights Reserved. |
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* Copyright (C) 2018 Andes Technology Corporation |
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* |
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* Perf_events support for RISC-V platforms. |
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* |
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* Since the spec. (as of now, Priv-Spec 1.10) does not provide enough |
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* functionality for perf event to fully work, this file provides |
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* the very basic framework only. |
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* |
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* For platform portings, please check Documentations/riscv/pmu.txt. |
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* |
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* The Copyright line includes x86 and tile ones. |
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*/ |
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#include <linux/kprobes.h> |
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#include <linux/kernel.h> |
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#include <linux/kdebug.h> |
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#include <linux/mutex.h> |
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#include <linux/bitmap.h> |
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#include <linux/irq.h> |
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#include <linux/perf_event.h> |
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#include <linux/atomic.h> |
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#include <linux/of.h> |
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#include <asm/perf_event.h> |
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static const struct riscv_pmu *riscv_pmu __read_mostly; |
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static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
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/* |
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* Hardware & cache maps and their methods |
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*/ |
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static const int riscv_hw_event_map[] = { |
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[PERF_COUNT_HW_CPU_CYCLES] = RISCV_PMU_CYCLE, |
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[PERF_COUNT_HW_INSTRUCTIONS] = RISCV_PMU_INSTRET, |
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[PERF_COUNT_HW_CACHE_REFERENCES] = RISCV_OP_UNSUPP, |
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[PERF_COUNT_HW_CACHE_MISSES] = RISCV_OP_UNSUPP, |
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = RISCV_OP_UNSUPP, |
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[PERF_COUNT_HW_BRANCH_MISSES] = RISCV_OP_UNSUPP, |
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[PERF_COUNT_HW_BUS_CYCLES] = RISCV_OP_UNSUPP, |
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}; |
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#define C(x) PERF_COUNT_HW_CACHE_##x |
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static const int riscv_cache_event_map[PERF_COUNT_HW_CACHE_MAX] |
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[PERF_COUNT_HW_CACHE_OP_MAX] |
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[PERF_COUNT_HW_CACHE_RESULT_MAX] = { |
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[C(L1D)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, |
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, |
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, |
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP, |
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}, |
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}, |
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[C(L1I)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, |
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, |
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, |
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP, |
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}, |
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}, |
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[C(LL)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, |
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, |
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, |
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP, |
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}, |
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}, |
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[C(DTLB)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, |
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, |
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, |
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP, |
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}, |
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}, |
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[C(ITLB)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, |
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, |
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, |
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP, |
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}, |
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}, |
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[C(BPU)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, |
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, |
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, |
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP, |
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}, |
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}, |
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}; |
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static int riscv_map_hw_event(u64 config) |
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{ |
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if (config >= riscv_pmu->max_events) |
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return -EINVAL; |
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return riscv_pmu->hw_events[config]; |
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} |
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static int riscv_map_cache_decode(u64 config, unsigned int *type, |
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unsigned int *op, unsigned int *result) |
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{ |
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return -ENOENT; |
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} |
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static int riscv_map_cache_event(u64 config) |
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{ |
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unsigned int type, op, result; |
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int err = -ENOENT; |
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int code; |
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err = riscv_map_cache_decode(config, &type, &op, &result); |
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if (!riscv_pmu->cache_events || err) |
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return err; |
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if (type >= PERF_COUNT_HW_CACHE_MAX || |
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op >= PERF_COUNT_HW_CACHE_OP_MAX || |
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result >= PERF_COUNT_HW_CACHE_RESULT_MAX) |
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return -EINVAL; |
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code = (*riscv_pmu->cache_events)[type][op][result]; |
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if (code == RISCV_OP_UNSUPP) |
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return -EINVAL; |
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return code; |
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} |
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/* |
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* Low-level functions: reading/writing counters |
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*/ |
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static inline u64 read_counter(int idx) |
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{ |
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u64 val = 0; |
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switch (idx) { |
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case RISCV_PMU_CYCLE: |
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val = csr_read(CSR_CYCLE); |
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break; |
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case RISCV_PMU_INSTRET: |
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val = csr_read(CSR_INSTRET); |
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break; |
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default: |
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WARN_ON_ONCE(idx < 0 || idx > RISCV_MAX_COUNTERS); |
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return -EINVAL; |
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} |
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return val; |
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} |
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static inline void write_counter(int idx, u64 value) |
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{ |
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/* currently not supported */ |
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WARN_ON_ONCE(1); |
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} |
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/* |
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* pmu->read: read and update the counter |
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* |
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* Other architectures' implementation often have a xxx_perf_event_update |
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* routine, which can return counter values when called in the IRQ, but |
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* return void when being called by the pmu->read method. |
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*/ |
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static void riscv_pmu_read(struct perf_event *event) |
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{ |
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struct hw_perf_event *hwc = &event->hw; |
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u64 prev_raw_count, new_raw_count; |
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u64 oldval; |
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int idx = hwc->idx; |
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u64 delta; |
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do { |
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prev_raw_count = local64_read(&hwc->prev_count); |
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new_raw_count = read_counter(idx); |
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oldval = local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
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new_raw_count); |
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} while (oldval != prev_raw_count); |
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/* |
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* delta is the value to update the counter we maintain in the kernel. |
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*/ |
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delta = (new_raw_count - prev_raw_count) & |
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((1ULL << riscv_pmu->counter_width) - 1); |
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local64_add(delta, &event->count); |
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/* |
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* Something like local64_sub(delta, &hwc->period_left) here is |
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* needed if there is an interrupt for perf. |
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*/ |
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} |
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/* |
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* State transition functions: |
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* |
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* stop()/start() & add()/del() |
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*/ |
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/* |
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* pmu->stop: stop the counter |
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*/ |
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static void riscv_pmu_stop(struct perf_event *event, int flags) |
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{ |
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struct hw_perf_event *hwc = &event->hw; |
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WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); |
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hwc->state |= PERF_HES_STOPPED; |
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if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
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riscv_pmu->pmu->read(event); |
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hwc->state |= PERF_HES_UPTODATE; |
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} |
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} |
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/* |
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* pmu->start: start the event. |
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*/ |
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static void riscv_pmu_start(struct perf_event *event, int flags) |
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{ |
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struct hw_perf_event *hwc = &event->hw; |
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if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
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return; |
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if (flags & PERF_EF_RELOAD) { |
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WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); |
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/* |
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* Set the counter to the period to the next interrupt here, |
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* if you have any. |
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*/ |
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} |
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hwc->state = 0; |
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perf_event_update_userpage(event); |
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/* |
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* Since we cannot write to counters, this serves as an initialization |
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* to the delta-mechanism in pmu->read(); otherwise, the delta would be |
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* wrong when pmu->read is called for the first time. |
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*/ |
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local64_set(&hwc->prev_count, read_counter(hwc->idx)); |
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} |
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/* |
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* pmu->add: add the event to PMU. |
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*/ |
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static int riscv_pmu_add(struct perf_event *event, int flags) |
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{ |
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struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
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struct hw_perf_event *hwc = &event->hw; |
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if (cpuc->n_events == riscv_pmu->num_counters) |
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return -ENOSPC; |
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/* |
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* We don't have general conunters, so no binding-event-to-counter |
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* process here. |
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* |
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* Indexing using hwc->config generally not works, since config may |
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* contain extra information, but here the only info we have in |
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* hwc->config is the event index. |
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*/ |
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hwc->idx = hwc->config; |
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cpuc->events[hwc->idx] = event; |
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cpuc->n_events++; |
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hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
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if (flags & PERF_EF_START) |
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riscv_pmu->pmu->start(event, PERF_EF_RELOAD); |
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return 0; |
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} |
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/* |
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* pmu->del: delete the event from PMU. |
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*/ |
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static void riscv_pmu_del(struct perf_event *event, int flags) |
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{ |
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struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
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struct hw_perf_event *hwc = &event->hw; |
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cpuc->events[hwc->idx] = NULL; |
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cpuc->n_events--; |
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riscv_pmu->pmu->stop(event, PERF_EF_UPDATE); |
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perf_event_update_userpage(event); |
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} |
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/* |
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* Interrupt: a skeletion for reference. |
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*/ |
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static DEFINE_MUTEX(pmc_reserve_mutex); |
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static irqreturn_t riscv_base_pmu_handle_irq(int irq_num, void *dev) |
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{ |
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return IRQ_NONE; |
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} |
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static int reserve_pmc_hardware(void) |
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{ |
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int err = 0; |
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mutex_lock(&pmc_reserve_mutex); |
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if (riscv_pmu->irq >= 0 && riscv_pmu->handle_irq) { |
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err = request_irq(riscv_pmu->irq, riscv_pmu->handle_irq, |
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IRQF_PERCPU, "riscv-base-perf", NULL); |
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} |
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mutex_unlock(&pmc_reserve_mutex); |
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return err; |
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} |
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static void release_pmc_hardware(void) |
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{ |
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mutex_lock(&pmc_reserve_mutex); |
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if (riscv_pmu->irq >= 0) |
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free_irq(riscv_pmu->irq, NULL); |
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mutex_unlock(&pmc_reserve_mutex); |
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} |
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/* |
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* Event Initialization/Finalization |
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*/ |
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static atomic_t riscv_active_events = ATOMIC_INIT(0); |
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static void riscv_event_destroy(struct perf_event *event) |
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{ |
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if (atomic_dec_return(&riscv_active_events) == 0) |
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release_pmc_hardware(); |
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} |
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static int riscv_event_init(struct perf_event *event) |
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{ |
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struct perf_event_attr *attr = &event->attr; |
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struct hw_perf_event *hwc = &event->hw; |
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int err; |
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int code; |
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if (atomic_inc_return(&riscv_active_events) == 1) { |
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err = reserve_pmc_hardware(); |
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if (err) { |
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pr_warn("PMC hardware not available\n"); |
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atomic_dec(&riscv_active_events); |
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return -EBUSY; |
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} |
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} |
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switch (event->attr.type) { |
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case PERF_TYPE_HARDWARE: |
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code = riscv_pmu->map_hw_event(attr->config); |
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break; |
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case PERF_TYPE_HW_CACHE: |
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code = riscv_pmu->map_cache_event(attr->config); |
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break; |
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case PERF_TYPE_RAW: |
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return -EOPNOTSUPP; |
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default: |
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return -ENOENT; |
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} |
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event->destroy = riscv_event_destroy; |
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if (code < 0) { |
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event->destroy(event); |
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return code; |
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} |
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/* |
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* idx is set to -1 because the index of a general event should not be |
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* decided until binding to some counter in pmu->add(). |
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* |
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* But since we don't have such support, later in pmu->add(), we just |
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* use hwc->config as the index instead. |
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*/ |
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hwc->config = code; |
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hwc->idx = -1; |
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return 0; |
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} |
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/* |
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* Initialization |
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*/ |
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static struct pmu min_pmu = { |
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.name = "riscv-base", |
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.event_init = riscv_event_init, |
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.add = riscv_pmu_add, |
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.del = riscv_pmu_del, |
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.start = riscv_pmu_start, |
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.stop = riscv_pmu_stop, |
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.read = riscv_pmu_read, |
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}; |
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static const struct riscv_pmu riscv_base_pmu = { |
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.pmu = &min_pmu, |
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.max_events = ARRAY_SIZE(riscv_hw_event_map), |
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.map_hw_event = riscv_map_hw_event, |
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.hw_events = riscv_hw_event_map, |
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.map_cache_event = riscv_map_cache_event, |
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.cache_events = &riscv_cache_event_map, |
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.counter_width = 63, |
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.num_counters = RISCV_BASE_COUNTERS + 0, |
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.handle_irq = &riscv_base_pmu_handle_irq, |
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/* This means this PMU has no IRQ. */ |
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.irq = -1, |
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}; |
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static const struct of_device_id riscv_pmu_of_ids[] = { |
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{.compatible = "riscv,base-pmu", .data = &riscv_base_pmu}, |
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{ /* sentinel value */ } |
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}; |
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static int __init init_hw_perf_events(void) |
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{ |
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struct device_node *node = of_find_node_by_type(NULL, "pmu"); |
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const struct of_device_id *of_id; |
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riscv_pmu = &riscv_base_pmu; |
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if (node) { |
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of_id = of_match_node(riscv_pmu_of_ids, node); |
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if (of_id) |
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riscv_pmu = of_id->data; |
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of_node_put(node); |
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} |
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perf_pmu_register(riscv_pmu->pmu, "cpu", PERF_TYPE_RAW); |
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return 0; |
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} |
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arch_initcall(init_hw_perf_events);
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