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456 lines
11 KiB
456 lines
11 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _ASM_IA64_BITOPS_H |
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#define _ASM_IA64_BITOPS_H |
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/* |
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* Copyright (C) 1998-2003 Hewlett-Packard Co |
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* David Mosberger-Tang <[email protected]> |
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* |
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* 02/06/02 find_next_bit() and find_first_bit() added from Erich Focht's ia64 |
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* O(1) scheduler patch |
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*/ |
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#ifndef _LINUX_BITOPS_H |
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#error only <linux/bitops.h> can be included directly |
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#endif |
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#include <linux/compiler.h> |
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#include <linux/types.h> |
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#include <asm/intrinsics.h> |
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#include <asm/barrier.h> |
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/** |
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* set_bit - Atomically set a bit in memory |
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* @nr: the bit to set |
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* @addr: the address to start counting from |
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* |
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* This function is atomic and may not be reordered. See __set_bit() |
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* if you do not require the atomic guarantees. |
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* Note that @nr may be almost arbitrarily large; this function is not |
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* restricted to acting on a single-word quantity. |
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* |
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* The address must be (at least) "long" aligned. |
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* Note that there are driver (e.g., eepro100) which use these operations to |
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* operate on hw-defined data-structures, so we can't easily change these |
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* operations to force a bigger alignment. |
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* |
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* bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). |
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*/ |
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static __inline__ void |
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set_bit (int nr, volatile void *addr) |
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{ |
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__u32 bit, old, new; |
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volatile __u32 *m; |
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CMPXCHG_BUGCHECK_DECL |
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m = (volatile __u32 *) addr + (nr >> 5); |
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bit = 1 << (nr & 31); |
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do { |
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CMPXCHG_BUGCHECK(m); |
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old = *m; |
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new = old | bit; |
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} while (cmpxchg_acq(m, old, new) != old); |
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} |
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/** |
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* __set_bit - Set a bit in memory |
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* @nr: the bit to set |
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* @addr: the address to start counting from |
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* |
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* Unlike set_bit(), this function is non-atomic and may be reordered. |
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* If it's called on the same region of memory simultaneously, the effect |
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* may be that only one operation succeeds. |
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*/ |
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static __inline__ void |
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__set_bit (int nr, volatile void *addr) |
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{ |
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*((__u32 *) addr + (nr >> 5)) |= (1 << (nr & 31)); |
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} |
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/** |
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* clear_bit - Clears a bit in memory |
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* @nr: Bit to clear |
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* @addr: Address to start counting from |
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* |
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* clear_bit() is atomic and may not be reordered. However, it does |
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* not contain a memory barrier, so if it is used for locking purposes, |
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* you should call smp_mb__before_atomic() and/or smp_mb__after_atomic() |
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* in order to ensure changes are visible on other processors. |
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*/ |
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static __inline__ void |
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clear_bit (int nr, volatile void *addr) |
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{ |
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__u32 mask, old, new; |
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volatile __u32 *m; |
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CMPXCHG_BUGCHECK_DECL |
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m = (volatile __u32 *) addr + (nr >> 5); |
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mask = ~(1 << (nr & 31)); |
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do { |
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CMPXCHG_BUGCHECK(m); |
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old = *m; |
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new = old & mask; |
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} while (cmpxchg_acq(m, old, new) != old); |
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} |
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/** |
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* clear_bit_unlock - Clears a bit in memory with release |
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* @nr: Bit to clear |
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* @addr: Address to start counting from |
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* |
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* clear_bit_unlock() is atomic and may not be reordered. It does |
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* contain a memory barrier suitable for unlock type operations. |
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*/ |
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static __inline__ void |
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clear_bit_unlock (int nr, volatile void *addr) |
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{ |
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__u32 mask, old, new; |
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volatile __u32 *m; |
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CMPXCHG_BUGCHECK_DECL |
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m = (volatile __u32 *) addr + (nr >> 5); |
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mask = ~(1 << (nr & 31)); |
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do { |
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CMPXCHG_BUGCHECK(m); |
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old = *m; |
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new = old & mask; |
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} while (cmpxchg_rel(m, old, new) != old); |
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} |
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/** |
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* __clear_bit_unlock - Non-atomically clears a bit in memory with release |
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* @nr: Bit to clear |
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* @addr: Address to start counting from |
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* |
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* Similarly to clear_bit_unlock, the implementation uses a store |
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* with release semantics. See also arch_spin_unlock(). |
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*/ |
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static __inline__ void |
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__clear_bit_unlock(int nr, void *addr) |
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{ |
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__u32 * const m = (__u32 *) addr + (nr >> 5); |
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__u32 const new = *m & ~(1 << (nr & 31)); |
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ia64_st4_rel_nta(m, new); |
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} |
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/** |
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* __clear_bit - Clears a bit in memory (non-atomic version) |
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* @nr: the bit to clear |
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* @addr: the address to start counting from |
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* |
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* Unlike clear_bit(), this function is non-atomic and may be reordered. |
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* If it's called on the same region of memory simultaneously, the effect |
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* may be that only one operation succeeds. |
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*/ |
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static __inline__ void |
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__clear_bit (int nr, volatile void *addr) |
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{ |
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*((__u32 *) addr + (nr >> 5)) &= ~(1 << (nr & 31)); |
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} |
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/** |
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* change_bit - Toggle a bit in memory |
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* @nr: Bit to toggle |
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* @addr: Address to start counting from |
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* |
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* change_bit() is atomic and may not be reordered. |
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* Note that @nr may be almost arbitrarily large; this function is not |
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* restricted to acting on a single-word quantity. |
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*/ |
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static __inline__ void |
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change_bit (int nr, volatile void *addr) |
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{ |
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__u32 bit, old, new; |
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volatile __u32 *m; |
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CMPXCHG_BUGCHECK_DECL |
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m = (volatile __u32 *) addr + (nr >> 5); |
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bit = (1 << (nr & 31)); |
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do { |
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CMPXCHG_BUGCHECK(m); |
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old = *m; |
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new = old ^ bit; |
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} while (cmpxchg_acq(m, old, new) != old); |
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} |
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/** |
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* __change_bit - Toggle a bit in memory |
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* @nr: the bit to toggle |
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* @addr: the address to start counting from |
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* |
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* Unlike change_bit(), this function is non-atomic and may be reordered. |
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* If it's called on the same region of memory simultaneously, the effect |
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* may be that only one operation succeeds. |
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*/ |
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static __inline__ void |
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__change_bit (int nr, volatile void *addr) |
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{ |
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*((__u32 *) addr + (nr >> 5)) ^= (1 << (nr & 31)); |
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} |
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/** |
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* test_and_set_bit - Set a bit and return its old value |
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* @nr: Bit to set |
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* @addr: Address to count from |
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* |
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* This operation is atomic and cannot be reordered. |
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* It also implies the acquisition side of the memory barrier. |
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*/ |
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static __inline__ int |
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test_and_set_bit (int nr, volatile void *addr) |
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{ |
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__u32 bit, old, new; |
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volatile __u32 *m; |
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CMPXCHG_BUGCHECK_DECL |
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m = (volatile __u32 *) addr + (nr >> 5); |
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bit = 1 << (nr & 31); |
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do { |
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CMPXCHG_BUGCHECK(m); |
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old = *m; |
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new = old | bit; |
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} while (cmpxchg_acq(m, old, new) != old); |
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return (old & bit) != 0; |
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} |
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/** |
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* test_and_set_bit_lock - Set a bit and return its old value for lock |
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* @nr: Bit to set |
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* @addr: Address to count from |
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* |
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* This is the same as test_and_set_bit on ia64 |
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*/ |
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#define test_and_set_bit_lock test_and_set_bit |
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/** |
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* __test_and_set_bit - Set a bit and return its old value |
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* @nr: Bit to set |
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* @addr: Address to count from |
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* |
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* This operation is non-atomic and can be reordered. |
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* If two examples of this operation race, one can appear to succeed |
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* but actually fail. You must protect multiple accesses with a lock. |
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*/ |
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static __inline__ int |
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__test_and_set_bit (int nr, volatile void *addr) |
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{ |
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__u32 *p = (__u32 *) addr + (nr >> 5); |
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__u32 m = 1 << (nr & 31); |
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int oldbitset = (*p & m) != 0; |
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*p |= m; |
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return oldbitset; |
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} |
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/** |
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* test_and_clear_bit - Clear a bit and return its old value |
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* @nr: Bit to clear |
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* @addr: Address to count from |
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* |
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* This operation is atomic and cannot be reordered. |
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* It also implies the acquisition side of the memory barrier. |
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*/ |
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static __inline__ int |
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test_and_clear_bit (int nr, volatile void *addr) |
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{ |
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__u32 mask, old, new; |
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volatile __u32 *m; |
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CMPXCHG_BUGCHECK_DECL |
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m = (volatile __u32 *) addr + (nr >> 5); |
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mask = ~(1 << (nr & 31)); |
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do { |
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CMPXCHG_BUGCHECK(m); |
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old = *m; |
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new = old & mask; |
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} while (cmpxchg_acq(m, old, new) != old); |
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return (old & ~mask) != 0; |
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} |
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/** |
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* __test_and_clear_bit - Clear a bit and return its old value |
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* @nr: Bit to clear |
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* @addr: Address to count from |
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* |
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* This operation is non-atomic and can be reordered. |
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* If two examples of this operation race, one can appear to succeed |
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* but actually fail. You must protect multiple accesses with a lock. |
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*/ |
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static __inline__ int |
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__test_and_clear_bit(int nr, volatile void * addr) |
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{ |
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__u32 *p = (__u32 *) addr + (nr >> 5); |
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__u32 m = 1 << (nr & 31); |
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int oldbitset = (*p & m) != 0; |
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*p &= ~m; |
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return oldbitset; |
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} |
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/** |
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* test_and_change_bit - Change a bit and return its old value |
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* @nr: Bit to change |
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* @addr: Address to count from |
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* |
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* This operation is atomic and cannot be reordered. |
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* It also implies the acquisition side of the memory barrier. |
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*/ |
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static __inline__ int |
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test_and_change_bit (int nr, volatile void *addr) |
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{ |
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__u32 bit, old, new; |
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volatile __u32 *m; |
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CMPXCHG_BUGCHECK_DECL |
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m = (volatile __u32 *) addr + (nr >> 5); |
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bit = (1 << (nr & 31)); |
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do { |
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CMPXCHG_BUGCHECK(m); |
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old = *m; |
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new = old ^ bit; |
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} while (cmpxchg_acq(m, old, new) != old); |
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return (old & bit) != 0; |
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} |
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/** |
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* __test_and_change_bit - Change a bit and return its old value |
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* @nr: Bit to change |
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* @addr: Address to count from |
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* |
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* This operation is non-atomic and can be reordered. |
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*/ |
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static __inline__ int |
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__test_and_change_bit (int nr, void *addr) |
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{ |
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__u32 old, bit = (1 << (nr & 31)); |
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__u32 *m = (__u32 *) addr + (nr >> 5); |
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old = *m; |
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*m = old ^ bit; |
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return (old & bit) != 0; |
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} |
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static __inline__ int |
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test_bit (int nr, const volatile void *addr) |
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{ |
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return 1 & (((const volatile __u32 *) addr)[nr >> 5] >> (nr & 31)); |
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} |
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/** |
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* ffz - find the first zero bit in a long word |
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* @x: The long word to find the bit in |
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* |
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* Returns the bit-number (0..63) of the first (least significant) zero bit. |
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* Undefined if no zero exists, so code should check against ~0UL first... |
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*/ |
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static inline unsigned long |
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ffz (unsigned long x) |
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{ |
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unsigned long result; |
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result = ia64_popcnt(x & (~x - 1)); |
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return result; |
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} |
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/** |
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* __ffs - find first bit in word. |
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* @x: The word to search |
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* |
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* Undefined if no bit exists, so code should check against 0 first. |
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*/ |
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static __inline__ unsigned long |
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__ffs (unsigned long x) |
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{ |
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unsigned long result; |
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result = ia64_popcnt((x-1) & ~x); |
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return result; |
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} |
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#ifdef __KERNEL__ |
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/* |
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* Return bit number of last (most-significant) bit set. Undefined |
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* for x==0. Bits are numbered from 0..63 (e.g., ia64_fls(9) == 3). |
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*/ |
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static inline unsigned long |
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ia64_fls (unsigned long x) |
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{ |
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long double d = x; |
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long exp; |
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exp = ia64_getf_exp(d); |
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return exp - 0xffff; |
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} |
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/* |
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* Find the last (most significant) bit set. Returns 0 for x==0 and |
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* bits are numbered from 1..32 (e.g., fls(9) == 4). |
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*/ |
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static inline int fls(unsigned int t) |
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{ |
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unsigned long x = t & 0xffffffffu; |
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if (!x) |
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return 0; |
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x |= x >> 1; |
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x |= x >> 2; |
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x |= x >> 4; |
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x |= x >> 8; |
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x |= x >> 16; |
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return ia64_popcnt(x); |
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} |
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/* |
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* Find the last (most significant) bit set. Undefined for x==0. |
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* Bits are numbered from 0..63 (e.g., __fls(9) == 3). |
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*/ |
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static inline unsigned long |
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__fls (unsigned long x) |
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{ |
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x |= x >> 1; |
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x |= x >> 2; |
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x |= x >> 4; |
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x |= x >> 8; |
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x |= x >> 16; |
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x |= x >> 32; |
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return ia64_popcnt(x) - 1; |
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} |
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#include <asm-generic/bitops/fls64.h> |
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#include <asm-generic/bitops/builtin-ffs.h> |
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/* |
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* hweightN: returns the hamming weight (i.e. the number |
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* of bits set) of a N-bit word |
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*/ |
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static __inline__ unsigned long __arch_hweight64(unsigned long x) |
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{ |
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unsigned long result; |
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result = ia64_popcnt(x); |
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return result; |
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} |
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#define __arch_hweight32(x) ((unsigned int) __arch_hweight64((x) & 0xfffffffful)) |
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#define __arch_hweight16(x) ((unsigned int) __arch_hweight64((x) & 0xfffful)) |
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#define __arch_hweight8(x) ((unsigned int) __arch_hweight64((x) & 0xfful)) |
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#include <asm-generic/bitops/const_hweight.h> |
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#endif /* __KERNEL__ */ |
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#include <asm-generic/bitops/find.h> |
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#ifdef __KERNEL__ |
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#include <asm-generic/bitops/le.h> |
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#include <asm-generic/bitops/ext2-atomic-setbit.h> |
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#include <asm-generic/bitops/sched.h> |
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#endif /* __KERNEL__ */ |
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#endif /* _ASM_IA64_BITOPS_H */
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