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627 lines
15 KiB
627 lines
15 KiB
/* |
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* Copyright 2016 ZTE Corporation. |
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* Copyright 2016 Linaro Ltd. |
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* |
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* This file is dual-licensed: you can use it either under the terms |
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* of the GPL or the X11 license, at your option. Note that this dual |
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* licensing only applies to this file, and not this project as a |
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* whole. |
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* |
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* a) This library is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of the |
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* License, or (at your option) any later version. |
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* |
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* This library is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* Or, alternatively, |
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* |
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* b) Permission is hereby granted, free of charge, to any person |
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* obtaining a copy of this software and associated documentation |
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* files (the "Software"), to deal in the Software without |
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* restriction, including without limitation the rights to use, |
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* copy, modify, merge, publish, distribute, sublicense, and/or |
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* sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following |
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* conditions: |
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* |
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* The above copyright notice and this permission notice shall be |
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* included in all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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*/ |
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#include <dt-bindings/input/input.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/gpio/gpio.h> |
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#include <dt-bindings/clock/zx296718-clock.h> |
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/ { |
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compatible = "zte,zx296718"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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interrupt-parent = <&gic>; |
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aliases { |
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gpio0 = &bgpio0; |
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gpio1 = &bgpio1; |
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gpio2 = &bgpio2; |
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gpio3 = &bgpio3; |
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gpio4 = &bgpio4; |
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gpio5 = &bgpio5; |
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gpio6 = &bgpio6; |
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serial0 = &uart0; |
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}; |
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cpus { |
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#address-cells = <2>; |
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#size-cells = <0>; |
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cpu-map { |
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cluster0 { |
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core0 { |
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cpu = <&cpu0>; |
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}; |
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core1 { |
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cpu = <&cpu1>; |
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}; |
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core2 { |
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cpu = <&cpu2>; |
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}; |
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core3 { |
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cpu = <&cpu3>; |
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}; |
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}; |
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}; |
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cpu0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x0>; |
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enable-method = "psci"; |
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clocks = <&topcrm A53_GATE>; |
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operating-points-v2 = <&cluster0_opp>; |
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}; |
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cpu1: cpu@1 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x1>; |
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enable-method = "psci"; |
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clocks = <&topcrm A53_GATE>; |
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operating-points-v2 = <&cluster0_opp>; |
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}; |
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cpu2: cpu@2 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x2>; |
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enable-method = "psci"; |
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clocks = <&topcrm A53_GATE>; |
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operating-points-v2 = <&cluster0_opp>; |
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}; |
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cpu3: cpu@3 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x3>; |
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enable-method = "psci"; |
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clocks = <&topcrm A53_GATE>; |
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operating-points-v2 = <&cluster0_opp>; |
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}; |
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}; |
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cluster0_opp: opp-table0 { |
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compatible = "operating-points-v2"; |
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opp-shared; |
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opp-500000000 { |
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opp-hz = /bits/ 64 <500000000>; |
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opp-microvolt = <866000>; |
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clock-latency-ns = <500000>; |
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}; |
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opp-648000000 { |
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opp-hz = /bits/ 64 <648000000>; |
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opp-microvolt = <866000>; |
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clock-latency-ns = <500000>; |
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}; |
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opp-800000000 { |
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opp-hz = /bits/ 64 <800000000>; |
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opp-microvolt = <888000>; |
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clock-latency-ns = <500000>; |
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}; |
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opp-1000000000 { |
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opp-hz = /bits/ 64 <1000000000>; |
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opp-microvolt = <898000>; |
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clock-latency-ns = <500000>; |
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}; |
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opp-1188000000 { |
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opp-hz = /bits/ 64 <1188000000>; |
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opp-microvolt = <1015000>; |
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clock-latency-ns = <500000>; |
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}; |
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}; |
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clk24k: clk-24k { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <24000>; |
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clock-output-names = "rtcclk"; |
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}; |
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osc32k: clk-osc32k { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <32000>; |
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clock-output-names = "osc32k"; |
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}; |
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osc12m: clk-osc12m { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <12000000>; |
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clock-output-names = "osc12m"; |
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}; |
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osc24m: clk-osc24m { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <24000000>; |
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clock-output-names = "osc24m"; |
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}; |
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osc25m: clk-osc25m { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <25000000>; |
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clock-output-names = "osc25m"; |
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}; |
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osc60m: clk-osc60m { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <60000000>; |
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clock-output-names = "osc60m"; |
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}; |
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osc99m: clk-osc99m { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <99000000>; |
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clock-output-names = "osc99m"; |
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}; |
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osc125m: clk-osc125m { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <125000000>; |
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clock-output-names = "osc125m"; |
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}; |
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osc198m: clk-osc198m { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <198000000>; |
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clock-output-names = "osc198m"; |
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}; |
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pll_audio: clk-pll-884m { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <884000000>; |
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clock-output-names = "pll_audio"; |
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}; |
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pll_ddr: clk-pll-932m { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <932000000>; |
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clock-output-names = "pll_ddr"; |
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}; |
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pll_hsic: clk-pll-960m { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <960000000>; |
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clock-output-names = "pll_hsic"; |
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}; |
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pll_mac: clk-pll-1000m { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <1000000000>; |
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clock-output-names = "pll_mac"; |
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}; |
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pll_mm0: clk-pll-1188m { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <1188000000>; |
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clock-output-names = "pll_mm0"; |
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}; |
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pll_mm1: clk-pll-1296m { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <1296000000>; |
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clock-output-names = "pll_mm1"; |
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}; |
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psci { |
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compatible = "arm,psci-1.0"; |
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method = "smc"; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
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}; |
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pmu { |
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compatible = "arm,cortex-a53-pmu"; |
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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gic: interrupt-controller@2a00000 { |
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compatible = "arm,gic-v3"; |
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#interrupt-cells = <3>; |
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#address-cells = <0>; |
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interrupt-controller; |
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reg = <0x02a00000 0x10000>, |
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<0x02b00000 0xc0000>; |
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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soc { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "simple-bus"; |
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ranges; |
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irdec: ir-decoder@111000 { |
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compatible = "zte,zx296718-irdec"; |
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reg = <0x111000 0x1000>; |
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interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
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status = "disabled"; |
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}; |
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aon_sysctrl: aon-sysctrl@116000 { |
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compatible = "zte,zx296718-aon-sysctrl", "syscon"; |
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reg = <0x116000 0x1000>; |
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}; |
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iocfg: pin-controller@119000 { |
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compatible = "zte,zx296718-iocfg"; |
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reg = <0x119000 0x1000>; |
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}; |
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uart0: uart@11f000 { |
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compatible = "arm,pl011", "arm,primecell"; |
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arm,primecell-periphid = <0x001feffe>; |
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reg = <0x11f000 0x1000>; |
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&osc24m>; |
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clock-names = "apb_pclk"; |
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status = "disabled"; |
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}; |
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sd0: mmc@1110000 { |
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compatible = "zte,zx296718-dw-mshc"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x01110000 0x1000>; |
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
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fifo-depth = <32>; |
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data-addr = <0x200>; |
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fifo-watermark-aligned; |
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bus-width = <4>; |
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clock-frequency = <50000000>; |
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clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>; |
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clock-names = "biu", "ciu"; |
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max-frequency = <50000000>; |
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cap-sdio-irq; |
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cap-sd-highspeed; |
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sd-uhs-sdr12; |
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sd-uhs-sdr25; |
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sd-uhs-sdr50; |
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sd-uhs-sdr104; |
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sd-uhs-ddr50; |
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status = "disabled"; |
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}; |
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sd1: mmc@1111000 { |
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compatible = "zte,zx296718-dw-mshc"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x01111000 0x1000>; |
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
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fifo-depth = <32>; |
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data-addr = <0x200>; |
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fifo-watermark-aligned; |
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bus-width = <4>; |
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clock-frequency = <167000000>; |
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clocks = <&topcrm SD1_AHB>, <&topcrm SD1_WCLK>; |
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clock-names = "biu", "ciu"; |
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max-frequency = <167000000>; |
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cap-sdio-irq; |
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cap-sd-highspeed; |
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status = "disabled"; |
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}; |
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dma: dma-controller@1460000 { |
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compatible = "zte,zx296702-dma"; |
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reg = <0x01460000 0x1000>; |
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&osc24m>; |
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clock-names = "dmaclk"; |
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#dma-cells = <1>; |
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dma-channels = <32>; |
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dma-requests = <32>; |
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}; |
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lsp0crm: clock-controller@1420000 { |
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compatible = "zte,zx296718-lsp0crm"; |
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reg = <0x01420000 0x1000>; |
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#clock-cells = <1>; |
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}; |
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bgpio0: gpio@142d000 { |
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compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; |
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reg = <0x142d000 0x40>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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gpio-ranges = <&pmm 0 48 16>; |
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-parent = <&gic>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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bgpio1: gpio@142d040 { |
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compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; |
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reg = <0x142d040 0x40>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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gpio-ranges = <&pmm 0 80 16>; |
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-parent = <&gic>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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bgpio2: gpio@142d080 { |
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compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; |
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reg = <0x142d080 0x40>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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gpio-ranges = <&pmm 0 80 3 |
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&pmm 3 32 4 |
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&pmm 7 83 9>; |
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-parent = <&gic>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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bgpio3: gpio@142d0c0 { |
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compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; |
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reg = <0x142d0c0 0x40>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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gpio-ranges = <&pmm 0 92 16>; |
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-parent = <&gic>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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bgpio4: gpio@142d100 { |
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compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; |
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reg = <0x142d100 0x40>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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gpio-ranges = <&pmm 0 108 12 |
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&pmm 12 121 4>; |
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-parent = <&gic>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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bgpio5: gpio@142d140 { |
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compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; |
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reg = <0x142d140 0x40>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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gpio-ranges = <&pmm 0 125 16>; |
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-parent = <&gic>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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bgpio6: gpio@142d180 { |
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compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; |
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reg = <0x142d180 0x40>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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gpio-ranges = <&pmm 0 141 2>; |
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-parent = <&gic>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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lsp1crm: clock-controller@1430000 { |
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compatible = "zte,zx296718-lsp1crm"; |
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reg = <0x01430000 0x1000>; |
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#clock-cells = <1>; |
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}; |
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pwm: pwm@1439000 { |
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compatible = "zte,zx296718-pwm"; |
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reg = <0x1439000 0x1000>; |
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clocks = <&lsp1crm LSP1_PWM_PCLK>, |
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<&lsp1crm LSP1_PWM_WCLK>; |
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clock-names = "pclk", "wclk"; |
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#pwm-cells = <3>; |
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status = "disabled"; |
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}; |
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vou: vou@1440000 { |
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compatible = "zte,zx296718-vou"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0 0x1440000 0x10000>; |
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dpc: dpc@0 { |
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compatible = "zte,zx296718-dpc"; |
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reg = <0x0000 0x1000>, <0x1000 0x1000>, |
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<0x5000 0x1000>, <0x6000 0x1000>, |
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<0xa000 0x1000>; |
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reg-names = "osd", "timing_ctrl", |
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"dtrc", "vou_ctrl", |
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"otfppu"; |
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>, |
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<&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>; |
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clock-names = "aclk", "ppu_wclk", |
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"main_wclk", "aux_wclk"; |
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}; |
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vga: vga@8000 { |
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compatible = "zte,zx296718-vga"; |
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reg = <0x8000 0x1000>; |
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&topcrm VGA_I2C_WCLK>; |
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clock-names = "i2c_wclk"; |
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zte,vga-power-control = <&sysctrl 0x170 0xe0>; |
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status = "disabled"; |
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}; |
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hdmi: hdmi@c000 { |
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compatible = "zte,zx296718-hdmi"; |
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reg = <0xc000 0x4000>; |
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interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>; |
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clocks = <&topcrm HDMI_OSC_CEC>, |
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<&topcrm HDMI_OSC_CLK>, |
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<&topcrm HDMI_XCLK>; |
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clock-names = "osc_cec", "osc_clk", "xclk"; |
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#sound-dai-cells = <0>; |
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status = "disabled"; |
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}; |
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tvenc: tvenc@2000 { |
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compatible = "zte,zx296718-tvenc"; |
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reg = <0x2000 0x1000>; |
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zte,tvenc-power-control = <&sysctrl 0x170 0x10>; |
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status = "disabled"; |
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}; |
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}; |
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topcrm: clock-controller@1461000 { |
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compatible = "zte,zx296718-topcrm"; |
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reg = <0x01461000 0x1000>; |
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#clock-cells = <1>; |
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}; |
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pmm: pin-controller@1462000 { |
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compatible = "zte,zx296718-pmm"; |
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reg = <0x1462000 0x1000>; |
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zte,auxiliary-controller = <&iocfg>; |
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}; |
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sysctrl: sysctrl@1463000 { |
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compatible = "zte,zx296718-sysctrl", "syscon"; |
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reg = <0x1463000 0x1000>; |
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}; |
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emmc: mmc@1470000{ |
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compatible = "zte,zx296718-dw-mshc"; |
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reg = <0x01470000 0x1000>; |
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
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zte,aon-syscon = <&aon_sysctrl>; |
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bus-width = <8>; |
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fifo-depth = <128>; |
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data-addr = <0x200>; |
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fifo-watermark-aligned; |
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clock-frequency = <167000000>; |
|
clocks = <&topcrm EMMC_NAND_AHB>, <&topcrm EMMC_WCLK>; |
|
clock-names = "biu", "ciu"; |
|
max-frequency = <167000000>; |
|
cap-mmc-highspeed; |
|
mmc-ddr-1_8v; |
|
mmc-hs200-1_8v; |
|
non-removable; |
|
disable-wp; |
|
status = "disabled"; |
|
}; |
|
|
|
audiocrm: clock-controller@1480000 { |
|
compatible = "zte,zx296718-audiocrm"; |
|
reg = <0x01480000 0x1000>; |
|
#clock-cells = <1>; |
|
}; |
|
|
|
i2s0: i2s@1482000 { |
|
compatible = "zte,zx296718-i2s", "zte,zx296702-i2s"; |
|
reg = <0x01482000 0x1000>; |
|
clocks = <&audiocrm AUDIO_I2S0_WCLK>, |
|
<&audiocrm AUDIO_I2S0_PCLK>; |
|
clock-names = "wclk", "pclk"; |
|
assigned-clocks = <&audiocrm I2S0_WCLK_MUX>; |
|
assigned-clock-parents = <&topcrm AUDIO_99M>; |
|
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
|
dmas = <&dma 22>, <&dma 23>; |
|
dma-names = "tx", "rx"; |
|
#sound-dai-cells = <0>; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c0: i2c@1486000 { |
|
compatible = "zte,zx296718-i2c"; |
|
reg = <0x01486000 0x1000>; |
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
clocks = <&audiocrm AUDIO_I2C0_WCLK>; |
|
clock-frequency = <1600000>; |
|
status = "disabled"; |
|
|
|
aud96p22: codec@22 { |
|
compatible = "zte,zx-aud96p22"; |
|
#sound-dai-cells = <0>; |
|
reg = <0x22>; |
|
}; |
|
}; |
|
|
|
spdif0: spdif@1488000 { |
|
compatible = "zte,zx296702-spdif"; |
|
reg = <0x1488000 0x1000>; |
|
clocks = <&audiocrm AUDIO_SPDIF0_WCLK>; |
|
clock-names = "tx"; |
|
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
|
#sound-dai-cells = <0>; |
|
dmas = <&dma 30>; |
|
dma-names = "tx"; |
|
status = "disabled"; |
|
}; |
|
}; |
|
};
|
|
|