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293 lines
5.1 KiB
293 lines
5.1 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* dts file for Xilinx ZynqMP ZCU104 |
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* |
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* (C) Copyright 2017 - 2020, Xilinx, Inc. |
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* |
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* Michal Simek <[email protected]> |
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*/ |
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/dts-v1/; |
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#include "zynqmp.dtsi" |
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#include "zynqmp-clk-ccf.dtsi" |
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#include <dt-bindings/gpio/gpio.h> |
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#include <dt-bindings/phy/phy.h> |
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/ { |
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model = "ZynqMP ZCU104 RevC"; |
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compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; |
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aliases { |
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ethernet0 = &gem3; |
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i2c0 = &i2c1; |
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mmc0 = &sdhci1; |
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rtc0 = &rtc; |
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serial0 = &uart0; |
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serial1 = &uart1; |
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serial2 = &dcc; |
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}; |
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chosen { |
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bootargs = "earlycon"; |
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stdout-path = "serial0:115200n8"; |
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}; |
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memory@0 { |
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device_type = "memory"; |
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reg = <0x0 0x0 0x0 0x80000000>; |
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}; |
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ina226 { |
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compatible = "iio-hwmon"; |
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io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; |
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}; |
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clock_8t49n287_5: clk125 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <125000000>; |
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}; |
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clock_8t49n287_2: clk26 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <26000000>; |
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}; |
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clock_8t49n287_3: clk27 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <27000000>; |
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}; |
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}; |
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&can1 { |
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status = "okay"; |
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}; |
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&dcc { |
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status = "okay"; |
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}; |
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&fpd_dma_chan1 { |
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status = "okay"; |
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}; |
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&fpd_dma_chan2 { |
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status = "okay"; |
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}; |
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&fpd_dma_chan3 { |
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status = "okay"; |
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}; |
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&fpd_dma_chan4 { |
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status = "okay"; |
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}; |
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&fpd_dma_chan5 { |
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status = "okay"; |
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}; |
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&fpd_dma_chan6 { |
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status = "okay"; |
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}; |
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&fpd_dma_chan7 { |
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status = "okay"; |
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}; |
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&fpd_dma_chan8 { |
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status = "okay"; |
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}; |
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&gem3 { |
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status = "okay"; |
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phy-handle = <&phy0>; |
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phy-mode = "rgmii-id"; |
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phy0: ethernet-phy@c { |
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reg = <0xc>; |
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ti,rx-internal-delay = <0x8>; |
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ti,tx-internal-delay = <0xa>; |
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ti,fifo-depth = <0x1>; |
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ti,dp83867-rxctrl-strap-quirk; |
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}; |
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}; |
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&gpio { |
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status = "okay"; |
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}; |
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&i2c1 { |
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status = "okay"; |
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clock-frequency = <400000>; |
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tca6416_u97: gpio@20 { |
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compatible = "ti,tca6416"; |
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reg = <0x20>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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/* |
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* IRQ not connected |
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* Lines: |
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* 0 - IRPS5401_ALERT_B |
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* 1 - HDMI_8T49N241_INT_ALM |
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* 2 - MAX6643_OT_B |
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* 3 - MAX6643_FANFAIL_B |
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* 5 - IIC_MUX_RESET_B |
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* 6 - GEM3_EXP_RESET_B |
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* 7 - FMC_LPC_PRSNT_M2C_B |
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* 4, 10 - 17 - not connected |
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*/ |
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}; |
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/* Another connection to this bus via PL i2c via PCA9306 - u45 */ |
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i2c-mux@74 { /* u34 */ |
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compatible = "nxp,pca9548"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x74>; |
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i2c@0 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0>; |
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/* |
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* IIC_EEPROM 1kB memory which uses 256B blocks |
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* where every block has different address. |
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* 0 - 256B address 0x54 |
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* 256B - 512B address 0x55 |
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* 512B - 768B address 0x56 |
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* 768B - 1024B address 0x57 |
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*/ |
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eeprom: eeprom@54 { /* u23 */ |
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compatible = "atmel,24c08"; |
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reg = <0x54>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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}; |
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}; |
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i2c@1 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <1>; |
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clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ |
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reg = <0x6c>; |
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}; |
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}; |
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i2c@2 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <2>; |
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irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ |
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compatible = "infineon,irps5401"; |
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reg = <0x43>; /* pmbus / i2c 0x13 */ |
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}; |
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irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ |
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compatible = "infineon,irps5401"; |
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reg = <0x44>; /* pmbus / i2c 0x14 */ |
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}; |
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}; |
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i2c@3 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <3>; |
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u183: ina226@40 { /* u183 */ |
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compatible = "ti,ina226"; |
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#io-channel-cells = <1>; |
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reg = <0x40>; |
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shunt-resistor = <5000>; |
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}; |
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}; |
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i2c@5 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <5>; |
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}; |
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i2c@7 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <7>; |
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}; |
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/* 4, 6 not connected */ |
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}; |
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}; |
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&qspi { |
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status = "okay"; |
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flash@0 { |
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compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0x0>; |
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}; |
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}; |
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&rtc { |
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status = "okay"; |
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}; |
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&psgtr { |
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status = "okay"; |
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/* nc, sata, usb3, dp */ |
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clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; |
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clock-names = "ref1", "ref2", "ref3"; |
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}; |
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&sata { |
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status = "okay"; |
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/* SATA OOB timing settings */ |
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ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; |
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ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; |
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ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; |
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ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; |
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ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; |
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ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; |
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ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; |
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ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; |
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phy-names = "sata-phy"; |
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phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; |
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}; |
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/* SD1 with level shifter */ |
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&sdhci1 { |
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status = "okay"; |
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no-1-8-v; |
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xlnx,mio-bank = <1>; |
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disable-wp; |
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}; |
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&uart0 { |
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status = "okay"; |
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}; |
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&uart1 { |
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status = "okay"; |
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}; |
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/* ULPI SMSC USB3320 */ |
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&usb0 { |
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status = "okay"; |
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dr_mode = "host"; |
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}; |
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&watchdog0 { |
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status = "okay"; |
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}; |
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&zynqmp_dpdma { |
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status = "okay"; |
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}; |
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&zynqmp_dpsub { |
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status = "okay"; |
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phy-names = "dp-phy0", "dp-phy1"; |
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phys = <&psgtr 1 PHY_TYPE_DP 0 3>, |
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<&psgtr 0 PHY_TYPE_DP 1 3>; |
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};
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