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239 lines
4.4 KiB
239 lines
4.4 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Clock specification for Xilinx ZynqMP |
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* |
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* (C) Copyright 2017 - 2019, Xilinx, Inc. |
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* |
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* Michal Simek <[email protected]> |
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*/ |
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#include <dt-bindings/clock/xlnx-zynqmp-clk.h> |
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/ { |
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pss_ref_clk: pss_ref_clk { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <33333333>; |
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}; |
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video_clk: video_clk { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <27000000>; |
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}; |
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pss_alt_ref_clk: pss_alt_ref_clk { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <0>; |
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}; |
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gt_crx_ref_clk: gt_crx_ref_clk { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <108000000>; |
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}; |
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aux_ref_clk: aux_ref_clk { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <27000000>; |
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}; |
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}; |
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&can0 { |
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clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&can1 { |
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clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&cpu0 { |
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clocks = <&zynqmp_clk ACPU>; |
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}; |
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&fpd_dma_chan1 { |
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&fpd_dma_chan2 { |
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&fpd_dma_chan3 { |
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&fpd_dma_chan4 { |
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&fpd_dma_chan5 { |
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&fpd_dma_chan6 { |
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&fpd_dma_chan7 { |
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&fpd_dma_chan8 { |
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&lpd_dma_chan1 { |
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&lpd_dma_chan2 { |
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&lpd_dma_chan3 { |
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&lpd_dma_chan4 { |
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&lpd_dma_chan5 { |
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&lpd_dma_chan6 { |
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&lpd_dma_chan7 { |
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&lpd_dma_chan8 { |
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&nand0 { |
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clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&gem0 { |
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, |
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<&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, |
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<&zynqmp_clk GEM_TSU>; |
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; |
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}; |
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&gem1 { |
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, |
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<&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, |
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<&zynqmp_clk GEM_TSU>; |
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; |
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}; |
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&gem2 { |
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, |
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<&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, |
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<&zynqmp_clk GEM_TSU>; |
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; |
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}; |
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&gem3 { |
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, |
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<&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, |
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<&zynqmp_clk GEM_TSU>; |
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; |
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}; |
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&gpio { |
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clocks = <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&i2c0 { |
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clocks = <&zynqmp_clk I2C0_REF>; |
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}; |
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&i2c1 { |
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clocks = <&zynqmp_clk I2C1_REF>; |
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}; |
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&pcie { |
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clocks = <&zynqmp_clk PCIE_REF>; |
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}; |
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&qspi { |
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clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&sata { |
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clocks = <&zynqmp_clk SATA_REF>; |
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}; |
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&sdhci0 { |
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clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&sdhci1 { |
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clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&spi0 { |
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clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&spi1 { |
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clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&ttc0 { |
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clocks = <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&ttc1 { |
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clocks = <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&ttc2 { |
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clocks = <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&ttc3 { |
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clocks = <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&uart0 { |
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clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&uart1 { |
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clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; |
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}; |
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&usb0 { |
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clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; |
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}; |
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&usb1 { |
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clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; |
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}; |
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&watchdog0 { |
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clocks = <&zynqmp_clk WDT>; |
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}; |
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&lpd_watchdog { |
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clocks = <&zynqmp_clk LPD_WDT>; |
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}; |
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&zynqmp_dpdma { |
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clocks = <&zynqmp_clk DPDMA_REF>; |
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}; |
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&zynqmp_dpsub { |
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clocks = <&zynqmp_clk TOPSW_LSBUS>, |
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<&zynqmp_clk DP_AUDIO_REF>, |
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<&zynqmp_clk DP_VIDEO_REF>; |
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};
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