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447 lines
10 KiB
447 lines
10 KiB
// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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/* |
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* Device Tree Source for the TMPV7708 |
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* |
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* (C) Copyright 2018 - 2020, Toshiba Corporation. |
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* (C) Copyright 2020, Nobuhiro Iwamatsu <[email protected]> |
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* |
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*/ |
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#include <dt-bindings/interrupt-controller/irq.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ |
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/ { |
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compatible = "toshiba,tmpv7708"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu-map { |
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cluster0 { |
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core0 { |
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cpu = <&cpu0>; |
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}; |
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core1 { |
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cpu = <&cpu1>; |
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}; |
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core2 { |
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cpu = <&cpu2>; |
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}; |
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core3 { |
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cpu = <&cpu3>; |
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}; |
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}; |
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cluster1 { |
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core0 { |
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cpu = <&cpu4>; |
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}; |
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core1 { |
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cpu = <&cpu5>; |
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}; |
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core2 { |
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cpu = <&cpu6>; |
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}; |
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core3 { |
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cpu = <&cpu7>; |
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}; |
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}; |
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}; |
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cpu0: cpu@0 { |
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compatible = "arm,cortex-a53"; |
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device_type = "cpu"; |
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enable-method = "spin-table"; |
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cpu-release-addr = <0x0 0x81100000>; |
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reg = <0x00>; |
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}; |
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cpu1: cpu@1 { |
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compatible = "arm,cortex-a53"; |
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device_type = "cpu"; |
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enable-method = "spin-table"; |
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cpu-release-addr = <0x0 0x81100000>; |
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reg = <0x01>; |
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}; |
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cpu2: cpu@2 { |
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compatible = "arm,cortex-a53"; |
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device_type = "cpu"; |
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enable-method = "spin-table"; |
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cpu-release-addr = <0x0 0x81100000>; |
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reg = <0x02>; |
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}; |
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cpu3: cpu@3 { |
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compatible = "arm,cortex-a53"; |
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device_type = "cpu"; |
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enable-method = "spin-table"; |
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cpu-release-addr = <0x0 0x81100000>; |
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reg = <0x03>; |
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}; |
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cpu4: cpu@100 { |
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compatible = "arm,cortex-a53"; |
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device_type = "cpu"; |
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enable-method = "spin-table"; |
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cpu-release-addr = <0x0 0x81100000>; |
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reg = <0x100>; |
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}; |
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cpu5: cpu@101 { |
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compatible = "arm,cortex-a53"; |
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device_type = "cpu"; |
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enable-method = "spin-table"; |
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cpu-release-addr = <0x0 0x81100000>; |
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reg = <0x101>; |
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}; |
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cpu6: cpu@102 { |
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compatible = "arm,cortex-a53"; |
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device_type = "cpu"; |
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enable-method = "spin-table"; |
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cpu-release-addr = <0x0 0x81100000>; |
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reg = <0x102>; |
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}; |
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cpu7: cpu@103 { |
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compatible = "arm,cortex-a53"; |
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device_type = "cpu"; |
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enable-method = "spin-table"; |
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cpu-release-addr = <0x0 0x81100000>; |
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reg = <0x103>; |
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}; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupt-parent = <&gic>; |
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interrupts = |
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<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; |
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}; |
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uart_clk: uart-clk { |
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compatible = "fixed-clock"; |
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clock-frequency = <150000000>; |
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#clock-cells = <0>; |
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}; |
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clk125mhz: clk125mhz { |
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compatible = "fixed-clock"; |
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clock-frequency = <125000000>; |
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#clock-cells = <0>; |
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clock-output-names = "clk125mhz"; |
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}; |
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clk300mhz: clk300mhz { |
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compatible = "fixed-clock"; |
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clock-frequency = <300000000>; |
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#clock-cells = <0>; |
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clock-output-names = "clk300mhz"; |
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}; |
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wdt_clk: wdt-clk { |
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compatible = "fixed-clock"; |
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clock-frequency = <150000000>; |
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#clock-cells = <0>; |
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}; |
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soc { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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compatible = "simple-bus"; |
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interrupt-parent = <&gic>; |
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ranges; |
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gic: interrupt-controller@24001000 { |
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compatible = "arm,gic-400"; |
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interrupt-controller; |
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#interrupt-cells = <3>; |
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; |
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reg = <0 0x24001000 0 0x1000>, |
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<0 0x24002000 0 0x2000>, |
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<0 0x24004000 0 0x2000>, |
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<0 0x24006000 0 0x2000>; |
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}; |
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pmux: pmux@24190000 { |
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compatible = "toshiba,tmpv7708-pinctrl"; |
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reg = <0 0x24190000 0 0x10000>; |
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}; |
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gpio: gpio@28020000 { |
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compatible = "toshiba,gpio-tmpv7708"; |
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reg = <0 0x28020000 0 0x1000>; |
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#gpio-cells = <0x2>; |
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gpio-ranges = <&pmux 0 0 32>; |
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gpio-controller; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupt-parent = <&gic>; |
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}; |
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uart0: serial@28200000 { |
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compatible = "arm,pl011", "arm,primecell"; |
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reg = <0 0x28200000 0 0x1000>; |
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&uart0_pins>; |
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status = "disabled"; |
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}; |
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uart1: serial@28201000 { |
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compatible = "arm,pl011", "arm,primecell"; |
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reg = <0 0x28201000 0 0x1000>; |
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interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&uart1_pins>; |
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status = "disabled"; |
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}; |
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uart2: serial@28202000 { |
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compatible = "arm,pl011", "arm,primecell"; |
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reg = <0 0x28202000 0 0x1000>; |
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interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&uart2_pins>; |
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status = "disabled"; |
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}; |
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uart3: serial@28203000 { |
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compatible = "arm,pl011", "arm,primecell"; |
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reg = <0 0x28203000 0 0x1000>; |
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&uart3_pins>; |
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status = "disabled"; |
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}; |
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i2c0: i2c@28030000 { |
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compatible = "snps,designware-i2c"; |
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reg = <0 0x28030000 0 0x1000>; |
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&i2c0_pins>; |
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clock-frequency = <400000>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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i2c1: i2c@28031000 { |
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compatible = "snps,designware-i2c"; |
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reg = <0 0x28031000 0 0x1000>; |
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interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&i2c1_pins>; |
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clock-frequency = <400000>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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i2c2: i2c@28032000 { |
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compatible = "snps,designware-i2c"; |
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reg = <0 0x28032000 0 0x1000>; |
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&i2c2_pins>; |
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clock-frequency = <400000>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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i2c3: i2c@28033000 { |
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compatible = "snps,designware-i2c"; |
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reg = <0 0x28033000 0 0x1000>; |
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&i2c3_pins>; |
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clock-frequency = <400000>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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i2c4: i2c@28034000 { |
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compatible = "snps,designware-i2c"; |
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reg = <0 0x28034000 0 0x1000>; |
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&i2c4_pins>; |
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clock-frequency = <400000>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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i2c5: i2c@28035000 { |
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compatible = "snps,designware-i2c"; |
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reg = <0 0x28035000 0 0x1000>; |
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&i2c5_pins>; |
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clock-frequency = <400000>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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i2c6: i2c@28036000 { |
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compatible = "snps,designware-i2c"; |
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reg = <0 0x28036000 0 0x1000>; |
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&i2c6_pins>; |
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clock-frequency = <400000>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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i2c7: i2c@28037000 { |
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compatible = "snps,designware-i2c"; |
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reg = <0 0x28037000 0 0x1000>; |
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interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&i2c7_pins>; |
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clock-frequency = <400000>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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i2c8: i2c@28038000 { |
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compatible = "snps,designware-i2c"; |
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reg = <0 0x28038000 0 0x1000>; |
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interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&i2c8_pins>; |
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clock-frequency = <400000>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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spi0: spi@28140000 { |
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compatible = "arm,pl022", "arm,primecell"; |
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reg = <0 0x28140000 0 0x1000>; |
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&spi0_pins>; |
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num-cs = <1>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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spi1: spi@28141000 { |
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compatible = "arm,pl022", "arm,primecell"; |
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reg = <0 0x28141000 0 0x1000>; |
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interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&spi1_pins>; |
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num-cs = <1>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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spi2: spi@28142000 { |
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compatible = "arm,pl022", "arm,primecell"; |
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reg = <0 0x28142000 0 0x1000>; |
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&spi2_pins>; |
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num-cs = <1>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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spi3: spi@28143000 { |
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compatible = "arm,pl022", "arm,primecell"; |
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reg = <0 0x28143000 0 0x1000>; |
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interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&spi3_pins>; |
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num-cs = <1>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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spi4: spi@28144000 { |
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compatible = "arm,pl022", "arm,primecell"; |
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reg = <0 0x28144000 0 0x1000>; |
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interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&spi4_pins>; |
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num-cs = <1>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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spi5: spi@28145000 { |
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compatible = "arm,pl022", "arm,primecell"; |
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reg = <0 0x28145000 0 0x1000>; |
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interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&spi5_pins>; |
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num-cs = <1>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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spi6: spi@28146000 { |
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compatible = "arm,pl022", "arm,primecell"; |
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reg = <0 0x28146000 0 0x1000>; |
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interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&spi6_pins>; |
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num-cs = <1>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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piether: ethernet@28000000 { |
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compatible = "toshiba,visconti-dwmac", "snps,dwmac-4.20a"; |
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reg = <0 0x28000000 0 0x10000>; |
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interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "macirq"; |
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snps,txpbl = <4>; |
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snps,rxpbl = <4>; |
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snps,tso; |
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status = "disabled"; |
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}; |
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wdt: wdt@28330000 { |
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compatible = "toshiba,visconti-wdt"; |
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reg = <0 0x28330000 0 0x1000>; |
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status = "disabled"; |
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}; |
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pwm: pwm@241c0000 { |
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compatible = "toshiba,visconti-pwm"; |
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reg = <0 0x241c0000 0 0x1000>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pwm_mux>; |
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#pwm-cells = <2>; |
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status = "disabled"; |
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}; |
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}; |
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}; |
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#include "tmpv7708_pins.dtsi"
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