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65 lines
1.2 KiB
65 lines
1.2 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Device Tree Source for AM642 SoC family in Dual core configuration |
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* |
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* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ |
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*/ |
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/dts-v1/; |
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#include "k3-am64.dtsi" |
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/ { |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu-map { |
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cluster0: cluster0 { |
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core0 { |
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cpu = <&cpu0>; |
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}; |
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core1 { |
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cpu = <&cpu1>; |
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}; |
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}; |
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}; |
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cpu0: cpu@0 { |
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compatible = "arm,cortex-a53"; |
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reg = <0x000>; |
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device_type = "cpu"; |
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enable-method = "psci"; |
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i-cache-size = <0x8000>; |
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i-cache-line-size = <64>; |
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i-cache-sets = <256>; |
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d-cache-size = <0x8000>; |
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d-cache-line-size = <64>; |
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d-cache-sets = <128>; |
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next-level-cache = <&L2_0>; |
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}; |
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cpu1: cpu@1 { |
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compatible = "arm,cortex-a53"; |
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reg = <0x001>; |
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device_type = "cpu"; |
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enable-method = "psci"; |
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i-cache-size = <0x8000>; |
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i-cache-line-size = <64>; |
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i-cache-sets = <256>; |
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d-cache-size = <0x8000>; |
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d-cache-line-size = <64>; |
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d-cache-sets = <128>; |
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next-level-cache = <&L2_0>; |
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}; |
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}; |
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L2_0: l2-cache0 { |
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compatible = "cache"; |
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cache-level = <2>; |
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cache-size = <0x40000>; |
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cache-line-size = <64>; |
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cache-sets = <512>; |
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}; |
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};
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